mirror of
https://github.com/jesseduffield/lazygit.git
synced 2024-12-14 11:23:09 +02:00
450 lines
9.1 KiB
ArmAsm
450 lines
9.1 KiB
ArmAsm
// Copyright 2019 The Go Authors. All rights reserved.
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// Use of this source code is governed by a BSD-style
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// license that can be found in the LICENSE file.
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// Based on CRYPTOGAMS code with the following comment:
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// # ====================================================================
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// # Written by Andy Polyakov <appro@openssl.org> for the OpenSSL
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// # project. The module is, however, dual licensed under OpenSSL and
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// # CRYPTOGAMS licenses depending on where you obtain it. For further
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// # details see http://www.openssl.org/~appro/cryptogams/.
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// # ====================================================================
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// Code for the perl script that generates the ppc64 assembler
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// can be found in the cryptogams repository at the link below. It is based on
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// the original from openssl.
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// https://github.com/dot-asm/cryptogams/commit/a60f5b50ed908e91
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// The differences in this and the original implementation are
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// due to the calling conventions and initialization of constants.
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// +build !gccgo,!purego
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#include "textflag.h"
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#define OUT R3
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#define INP R4
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#define LEN R5
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#define KEY R6
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#define CNT R7
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#define TMP R15
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#define CONSTBASE R16
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#define BLOCKS R17
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DATA consts<>+0x00(SB)/8, $0x3320646e61707865
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DATA consts<>+0x08(SB)/8, $0x6b20657479622d32
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DATA consts<>+0x10(SB)/8, $0x0000000000000001
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DATA consts<>+0x18(SB)/8, $0x0000000000000000
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DATA consts<>+0x20(SB)/8, $0x0000000000000004
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DATA consts<>+0x28(SB)/8, $0x0000000000000000
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DATA consts<>+0x30(SB)/8, $0x0a0b08090e0f0c0d
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DATA consts<>+0x38(SB)/8, $0x0203000106070405
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DATA consts<>+0x40(SB)/8, $0x090a0b080d0e0f0c
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DATA consts<>+0x48(SB)/8, $0x0102030005060704
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DATA consts<>+0x50(SB)/8, $0x6170786561707865
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DATA consts<>+0x58(SB)/8, $0x6170786561707865
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DATA consts<>+0x60(SB)/8, $0x3320646e3320646e
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DATA consts<>+0x68(SB)/8, $0x3320646e3320646e
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DATA consts<>+0x70(SB)/8, $0x79622d3279622d32
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DATA consts<>+0x78(SB)/8, $0x79622d3279622d32
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DATA consts<>+0x80(SB)/8, $0x6b2065746b206574
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DATA consts<>+0x88(SB)/8, $0x6b2065746b206574
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DATA consts<>+0x90(SB)/8, $0x0000000100000000
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DATA consts<>+0x98(SB)/8, $0x0000000300000002
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GLOBL consts<>(SB), RODATA, $0xa0
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//func chaCha20_ctr32_vsx(out, inp *byte, len int, key *[8]uint32, counter *uint32)
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TEXT ·chaCha20_ctr32_vsx(SB),NOSPLIT,$64-40
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MOVD out+0(FP), OUT
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MOVD inp+8(FP), INP
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MOVD len+16(FP), LEN
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MOVD key+24(FP), KEY
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MOVD counter+32(FP), CNT
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// Addressing for constants
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MOVD $consts<>+0x00(SB), CONSTBASE
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MOVD $16, R8
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MOVD $32, R9
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MOVD $48, R10
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MOVD $64, R11
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SRD $6, LEN, BLOCKS
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// V16
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LXVW4X (CONSTBASE)(R0), VS48
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ADD $80,CONSTBASE
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// Load key into V17,V18
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LXVW4X (KEY)(R0), VS49
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LXVW4X (KEY)(R8), VS50
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// Load CNT, NONCE into V19
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LXVW4X (CNT)(R0), VS51
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// Clear V27
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VXOR V27, V27, V27
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// V28
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LXVW4X (CONSTBASE)(R11), VS60
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// splat slot from V19 -> V26
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VSPLTW $0, V19, V26
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VSLDOI $4, V19, V27, V19
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VSLDOI $12, V27, V19, V19
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VADDUWM V26, V28, V26
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MOVD $10, R14
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MOVD R14, CTR
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loop_outer_vsx:
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// V0, V1, V2, V3
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LXVW4X (R0)(CONSTBASE), VS32
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LXVW4X (R8)(CONSTBASE), VS33
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LXVW4X (R9)(CONSTBASE), VS34
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LXVW4X (R10)(CONSTBASE), VS35
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// splat values from V17, V18 into V4-V11
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VSPLTW $0, V17, V4
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VSPLTW $1, V17, V5
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VSPLTW $2, V17, V6
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VSPLTW $3, V17, V7
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VSPLTW $0, V18, V8
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VSPLTW $1, V18, V9
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VSPLTW $2, V18, V10
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VSPLTW $3, V18, V11
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// VOR
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VOR V26, V26, V12
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// splat values from V19 -> V13, V14, V15
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VSPLTW $1, V19, V13
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VSPLTW $2, V19, V14
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VSPLTW $3, V19, V15
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// splat const values
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VSPLTISW $-16, V27
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VSPLTISW $12, V28
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VSPLTISW $8, V29
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VSPLTISW $7, V30
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loop_vsx:
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VADDUWM V0, V4, V0
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VADDUWM V1, V5, V1
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VADDUWM V2, V6, V2
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VADDUWM V3, V7, V3
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VXOR V12, V0, V12
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VXOR V13, V1, V13
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VXOR V14, V2, V14
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VXOR V15, V3, V15
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VRLW V12, V27, V12
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VRLW V13, V27, V13
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VRLW V14, V27, V14
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VRLW V15, V27, V15
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VADDUWM V8, V12, V8
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VADDUWM V9, V13, V9
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VADDUWM V10, V14, V10
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VADDUWM V11, V15, V11
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VXOR V4, V8, V4
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VXOR V5, V9, V5
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VXOR V6, V10, V6
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VXOR V7, V11, V7
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VRLW V4, V28, V4
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VRLW V5, V28, V5
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VRLW V6, V28, V6
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VRLW V7, V28, V7
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VADDUWM V0, V4, V0
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VADDUWM V1, V5, V1
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VADDUWM V2, V6, V2
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VADDUWM V3, V7, V3
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VXOR V12, V0, V12
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VXOR V13, V1, V13
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VXOR V14, V2, V14
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VXOR V15, V3, V15
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VRLW V12, V29, V12
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VRLW V13, V29, V13
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VRLW V14, V29, V14
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VRLW V15, V29, V15
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VADDUWM V8, V12, V8
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VADDUWM V9, V13, V9
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VADDUWM V10, V14, V10
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VADDUWM V11, V15, V11
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VXOR V4, V8, V4
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VXOR V5, V9, V5
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VXOR V6, V10, V6
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VXOR V7, V11, V7
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VRLW V4, V30, V4
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VRLW V5, V30, V5
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VRLW V6, V30, V6
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VRLW V7, V30, V7
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VADDUWM V0, V5, V0
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VADDUWM V1, V6, V1
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VADDUWM V2, V7, V2
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VADDUWM V3, V4, V3
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VXOR V15, V0, V15
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VXOR V12, V1, V12
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VXOR V13, V2, V13
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VXOR V14, V3, V14
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VRLW V15, V27, V15
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VRLW V12, V27, V12
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VRLW V13, V27, V13
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VRLW V14, V27, V14
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VADDUWM V10, V15, V10
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VADDUWM V11, V12, V11
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VADDUWM V8, V13, V8
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VADDUWM V9, V14, V9
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VXOR V5, V10, V5
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VXOR V6, V11, V6
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VXOR V7, V8, V7
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VXOR V4, V9, V4
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VRLW V5, V28, V5
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VRLW V6, V28, V6
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VRLW V7, V28, V7
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VRLW V4, V28, V4
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VADDUWM V0, V5, V0
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VADDUWM V1, V6, V1
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VADDUWM V2, V7, V2
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VADDUWM V3, V4, V3
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VXOR V15, V0, V15
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VXOR V12, V1, V12
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VXOR V13, V2, V13
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VXOR V14, V3, V14
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VRLW V15, V29, V15
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VRLW V12, V29, V12
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VRLW V13, V29, V13
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VRLW V14, V29, V14
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VADDUWM V10, V15, V10
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VADDUWM V11, V12, V11
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VADDUWM V8, V13, V8
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VADDUWM V9, V14, V9
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VXOR V5, V10, V5
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VXOR V6, V11, V6
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VXOR V7, V8, V7
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VXOR V4, V9, V4
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VRLW V5, V30, V5
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VRLW V6, V30, V6
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VRLW V7, V30, V7
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VRLW V4, V30, V4
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BC 16, LT, loop_vsx
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VADDUWM V12, V26, V12
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WORD $0x13600F8C // VMRGEW V0, V1, V27
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WORD $0x13821F8C // VMRGEW V2, V3, V28
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WORD $0x10000E8C // VMRGOW V0, V1, V0
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WORD $0x10421E8C // VMRGOW V2, V3, V2
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WORD $0x13A42F8C // VMRGEW V4, V5, V29
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WORD $0x13C63F8C // VMRGEW V6, V7, V30
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XXPERMDI VS32, VS34, $0, VS33
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XXPERMDI VS32, VS34, $3, VS35
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XXPERMDI VS59, VS60, $0, VS32
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XXPERMDI VS59, VS60, $3, VS34
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WORD $0x10842E8C // VMRGOW V4, V5, V4
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WORD $0x10C63E8C // VMRGOW V6, V7, V6
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WORD $0x13684F8C // VMRGEW V8, V9, V27
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WORD $0x138A5F8C // VMRGEW V10, V11, V28
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XXPERMDI VS36, VS38, $0, VS37
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XXPERMDI VS36, VS38, $3, VS39
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XXPERMDI VS61, VS62, $0, VS36
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XXPERMDI VS61, VS62, $3, VS38
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WORD $0x11084E8C // VMRGOW V8, V9, V8
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WORD $0x114A5E8C // VMRGOW V10, V11, V10
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WORD $0x13AC6F8C // VMRGEW V12, V13, V29
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WORD $0x13CE7F8C // VMRGEW V14, V15, V30
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XXPERMDI VS40, VS42, $0, VS41
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XXPERMDI VS40, VS42, $3, VS43
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XXPERMDI VS59, VS60, $0, VS40
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XXPERMDI VS59, VS60, $3, VS42
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WORD $0x118C6E8C // VMRGOW V12, V13, V12
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WORD $0x11CE7E8C // VMRGOW V14, V15, V14
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VSPLTISW $4, V27
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VADDUWM V26, V27, V26
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XXPERMDI VS44, VS46, $0, VS45
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XXPERMDI VS44, VS46, $3, VS47
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XXPERMDI VS61, VS62, $0, VS44
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XXPERMDI VS61, VS62, $3, VS46
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VADDUWM V0, V16, V0
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VADDUWM V4, V17, V4
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VADDUWM V8, V18, V8
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VADDUWM V12, V19, V12
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CMPU LEN, $64
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BLT tail_vsx
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// Bottom of loop
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LXVW4X (INP)(R0), VS59
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LXVW4X (INP)(R8), VS60
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LXVW4X (INP)(R9), VS61
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LXVW4X (INP)(R10), VS62
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VXOR V27, V0, V27
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VXOR V28, V4, V28
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VXOR V29, V8, V29
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VXOR V30, V12, V30
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STXVW4X VS59, (OUT)(R0)
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STXVW4X VS60, (OUT)(R8)
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ADD $64, INP
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STXVW4X VS61, (OUT)(R9)
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ADD $-64, LEN
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STXVW4X VS62, (OUT)(R10)
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ADD $64, OUT
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BEQ done_vsx
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VADDUWM V1, V16, V0
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VADDUWM V5, V17, V4
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VADDUWM V9, V18, V8
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VADDUWM V13, V19, V12
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CMPU LEN, $64
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BLT tail_vsx
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LXVW4X (INP)(R0), VS59
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LXVW4X (INP)(R8), VS60
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LXVW4X (INP)(R9), VS61
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LXVW4X (INP)(R10), VS62
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VXOR V27, V0, V27
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VXOR V28, V4, V28
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VXOR V29, V8, V29
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VXOR V30, V12, V30
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STXVW4X VS59, (OUT)(R0)
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STXVW4X VS60, (OUT)(R8)
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ADD $64, INP
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STXVW4X VS61, (OUT)(R9)
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ADD $-64, LEN
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STXVW4X VS62, (OUT)(V10)
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ADD $64, OUT
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BEQ done_vsx
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VADDUWM V2, V16, V0
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VADDUWM V6, V17, V4
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VADDUWM V10, V18, V8
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VADDUWM V14, V19, V12
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CMPU LEN, $64
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BLT tail_vsx
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LXVW4X (INP)(R0), VS59
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LXVW4X (INP)(R8), VS60
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LXVW4X (INP)(R9), VS61
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LXVW4X (INP)(R10), VS62
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VXOR V27, V0, V27
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VXOR V28, V4, V28
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VXOR V29, V8, V29
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VXOR V30, V12, V30
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STXVW4X VS59, (OUT)(R0)
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STXVW4X VS60, (OUT)(R8)
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ADD $64, INP
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STXVW4X VS61, (OUT)(R9)
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ADD $-64, LEN
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STXVW4X VS62, (OUT)(R10)
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ADD $64, OUT
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BEQ done_vsx
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VADDUWM V3, V16, V0
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VADDUWM V7, V17, V4
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VADDUWM V11, V18, V8
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VADDUWM V15, V19, V12
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CMPU LEN, $64
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BLT tail_vsx
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LXVW4X (INP)(R0), VS59
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LXVW4X (INP)(R8), VS60
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LXVW4X (INP)(R9), VS61
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LXVW4X (INP)(R10), VS62
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VXOR V27, V0, V27
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VXOR V28, V4, V28
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VXOR V29, V8, V29
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VXOR V30, V12, V30
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STXVW4X VS59, (OUT)(R0)
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STXVW4X VS60, (OUT)(R8)
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ADD $64, INP
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STXVW4X VS61, (OUT)(R9)
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ADD $-64, LEN
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STXVW4X VS62, (OUT)(R10)
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ADD $64, OUT
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MOVD $10, R14
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MOVD R14, CTR
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BNE loop_outer_vsx
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done_vsx:
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// Increment counter by number of 64 byte blocks
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MOVD (CNT), R14
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ADD BLOCKS, R14
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MOVD R14, (CNT)
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RET
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tail_vsx:
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ADD $32, R1, R11
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MOVD LEN, CTR
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// Save values on stack to copy from
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STXVW4X VS32, (R11)(R0)
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STXVW4X VS36, (R11)(R8)
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STXVW4X VS40, (R11)(R9)
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STXVW4X VS44, (R11)(R10)
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ADD $-1, R11, R12
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ADD $-1, INP
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ADD $-1, OUT
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looptail_vsx:
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// Copying the result to OUT
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// in bytes.
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MOVBZU 1(R12), KEY
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MOVBZU 1(INP), TMP
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XOR KEY, TMP, KEY
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MOVBU KEY, 1(OUT)
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BC 16, LT, looptail_vsx
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// Clear the stack values
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STXVW4X VS48, (R11)(R0)
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STXVW4X VS48, (R11)(R8)
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STXVW4X VS48, (R11)(R9)
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STXVW4X VS48, (R11)(R10)
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BR done_vsx
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