extrasyn: Add highlighters for JSON, Verilog, VHDL. Kindly provided by MRisco, issue #18248. Shorten menu in demo program.

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git-svn-id: https://svn.code.sf.net/p/lazarus-ccr/svn@8075 8e941d3f-bd1b-0410-a28a-d453659cc2b4

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wp_xxyyzz

2021-08-18 21:27:43 +00:00

parent 89d246386d

commit f0bada71d3

23 changed files with 3215 additions and 462 deletions

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