diff --git a/src/exercises/bare-metal/rtc/src/gicv3.rs b/src/exercises/bare-metal/rtc/src/gicv3.rs
index bd5d5f89..eb9b5beb 100644
--- a/src/exercises/bare-metal/rtc/src/gicv3.rs
+++ b/src/exercises/bare-metal/rtc/src/gicv3.rs
@@ -17,6 +17,7 @@
 use bitflags::bitflags;
 use core::{
     arch::asm,
+    fmt::{self, Debug, Formatter},
     hint::spin_loop,
     mem::size_of,
     ptr::{addr_of, addr_of_mut},
@@ -56,7 +57,7 @@ macro_rules! write_sysreg {
 const SGI_OFFSET: usize = 0x10000;
 
 /// An interrupt ID.
-#[derive(Copy, Clone, Debug, Eq, Ord, PartialOrd, PartialEq)]
+#[derive(Copy, Clone, Eq, Ord, PartialOrd, PartialEq)]
 pub struct IntId(u32);
 
 impl IntId {
@@ -102,6 +103,20 @@ impl IntId {
     }
 }
 
+impl Debug for IntId {
+    fn fmt(&self, f: &mut Formatter) -> fmt::Result {
+        if self.0 < Self::PPI_START {
+            write!(f, "SGI {}", self.0 - Self::SGI_START)
+        } else if self.0 < Self::SPI_START {
+            write!(f, "PPI {}", self.0 - Self::PPI_START)
+        } else if self.0 < Self::SPECIAL_START {
+            write!(f, "SPI {}", self.0 - Self::SPI_START)
+        } else {
+            write!(f, "Special IntId {}", self.0)
+        }
+    }
+}
+
 impl From<IntId> for u32 {
     fn from(intid: IntId) -> Self {
         intid.0