diff --git a/.github/typos.toml b/.github/typos.toml new file mode 100644 index 00000000..7283f162 --- /dev/null +++ b/.github/typos.toml @@ -0,0 +1,16 @@ +[default.extend-identifiers] +# False positives. +mis = "mis" +MIS = "MIS" +inout = "inout" +BARs = "BARs" + +[type.po] +# Localized content should not be checked for typos. English +# in these files should be validated manually. +extend-glob = ["*.po"] +check-file = false + +[files] +# Typos in third party packages should be fixed upstream. +extend-exclude = ["third_party/*"] diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index 681e950f..1a94aa1c 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -24,6 +24,11 @@ jobs: - name: Check formatting uses: dprint/check@v2.2 + - name: Check for typos + uses: crate-ci/typos@v1.16.9 + with: + config: ./.github/typos.toml + cargo: strategy: matrix: diff --git a/po/uk.po b/po/uk.po index fed866c5..9471f5e9 100644 --- a/po/uk.po +++ b/po/uk.po @@ -3669,7 +3669,7 @@ msgstr "" #: src/exercises/day-1/for-loops.md:102 msgid "" -"An implicit array copy would have occured. Since `i32` is a copy type, then " +"An implicit array copy would have occurred. Since `i32` is a copy type, then " "`[i32; 3]` is also a copy type." msgstr "" @@ -13791,7 +13791,7 @@ msgstr "" msgid "" "If it were running in a VM, this can lead to cache coherency issues. The " "problem is that the VM is accessing memory directly with the cache disabled, " -"while the host has cachable aliases to the same memory. Even if the host " +"while the host has cacheable aliases to the same memory. Even if the host " "doesn't explicitly access the memory, speculative accesses can lead to cache " "fills, and then changes from one or the other will get lost when the cache " "is cleaned or the VM enables the cache. (Cache is keyed by physical address, " @@ -14778,7 +14778,7 @@ msgstr "" msgid "" "If it were running in a VM, this can lead to cache coherency issues. The " "problem is that the VM is accessing memory directly with the cache disabled, " -"while the host has cachable aliases to the same memory. Even if the host " +"while the host has cacheable aliases to the same memory. Even if the host " "doesn't explicitly access the memory, speculative accesses can lead to cache " "fills, and then changes from one or the other will get lost. Again this is " "alright in this particular case (running directly on the hardware with no " diff --git a/src/async/pitfalls/cancellation.md b/src/async/pitfalls/cancellation.md index 8969b7f4..cf4aba18 100644 --- a/src/async/pitfalls/cancellation.md +++ b/src/async/pitfalls/cancellation.md @@ -79,7 +79,7 @@ async fn main() -> std::io::Result<()> { * Whenever the `tick()` branch finishes first, `next()` and its `buf` are dropped. - * `LinesReader` can be made cancellation-safe by makeing `buf` part of the struct: + * `LinesReader` can be made cancellation-safe by making `buf` part of the struct: ```rust,compile_fail struct LinesReader { stream: DuplexStream, diff --git a/src/bare-metal/aps/entry-point.md b/src/bare-metal/aps/entry-point.md index 91dbaa43..b40005d1 100644 --- a/src/bare-metal/aps/entry-point.md +++ b/src/bare-metal/aps/entry-point.md @@ -21,7 +21,7 @@ Before we can start running Rust code, we need to do some initialisation. which sets `+strict-align` to prevent the compiler generating unaligned accesses, so it should be fine in this case, but this is not necessarily the case in general. * If it were running in a VM, this can lead to cache coherency issues. The problem is that the VM - is accessing memory directly with the cache disabled, while the host has cachable aliases to the + is accessing memory directly with the cache disabled, while the host has cacheable aliases to the same memory. Even if the host doesn't explicitly access the memory, speculative accesses can lead to cache fills, and then changes from one or the other will get lost when the cache is cleaned or the VM enables the cache. (Cache is keyed by physical address, not VA or IPA.) diff --git a/src/bare-metal/aps/other-projects.md b/src/bare-metal/aps/other-projects.md index ed0af1b4..6f021790 100644 --- a/src/bare-metal/aps/other-projects.md +++ b/src/bare-metal/aps/other-projects.md @@ -20,7 +20,7 @@ which sets `+strict-align` to prevent the compiler generating unaligned accesses so it should be alright, but this is not necessarily the case in general. * If it were running in a VM, this can lead to cache coherency issues. The problem is that the VM - is accessing memory directly with the cache disabled, while the host has cachable aliases to the + is accessing memory directly with the cache disabled, while the host has cacheable aliases to the same memory. Even if the host doesn't explicitly access the memory, speculative accesses can lead to cache fills, and then changes from one or the other will get lost. Again this is alright in this particular case (running directly on the hardware with no hypervisor), but isn't a good diff --git a/src/bare-metal/aps/uart.md b/src/bare-metal/aps/uart.md index e18933fa..9c868bff 100644 --- a/src/bare-metal/aps/uart.md +++ b/src/bare-metal/aps/uart.md @@ -19,6 +19,6 @@ The QEMU 'virt' machine has a [PL011][1] UART, so let's write a driver for that. * This is a common pattern for writing safe wrappers of unsafe code: moving the burden of proof for soundness from a large number of places to a smaller number of places. - + [1]: https://developer.arm.com/documentation/ddi0183/g diff --git a/src/exercises/day-1/for-loops.md b/src/exercises/day-1/for-loops.md index de45c319..c1bfa69e 100644 --- a/src/exercises/day-1/for-loops.md +++ b/src/exercises/day-1/for-loops.md @@ -86,7 +86,7 @@ Without the `&`... * The loop would have been one that consumes the array. This is a change [introduced in the 2021 Edition](https://doc.rust-lang.org/edition-guide/rust-2021/IntoIterator-for-arrays.html). -* An implicit array copy would have occured. Since `i32` is a copy type, then +* An implicit array copy would have occurred. Since `i32` is a copy type, then `[i32; 3]` is also a copy type.