diff --git a/src/exercises/bare-metal/rtc.md b/src/exercises/bare-metal/rtc.md
index 9a12f42a..a49056f5 100644
--- a/src/exercises/bare-metal/rtc.md
+++ b/src/exercises/bare-metal/rtc.md
@@ -7,6 +7,8 @@ should write a driver for it.
    date/time formatting.
 2. Use the match register and raw interrupt status to busy-wait until a given time, e.g. 3 seconds
    in the future. (Call [`core::hint::spin_loop`][3] inside the loop.)
+3. _Extension if you have time:_ Enable and handle the interrupt generated by the RTC match. You can
+   use the driver provided in the `gicv3` module to configure the Arm Generic Interrupt Controller.
 
 Download the [exercise template](../../comprehensive-rust-exercises.zip) and look in the `rtc`
 directory for the following files.
@@ -29,7 +31,7 @@ directory for the following files.
 {{#include rtc/src/main.rs:main_end}}
 ```
 
-`src/exceptions.rs` (you shouldn't need to change this):
+`src/exceptions.rs` (you should only need to change this for the 3rd part of the exercise):
 
 <!-- File src/exceptions.rs -->
 
diff --git a/src/exercises/bare-metal/rtc/src/main.rs b/src/exercises/bare-metal/rtc/src/main.rs
index d1b12e01..8ecdc10b 100644
--- a/src/exercises/bare-metal/rtc/src/main.rs
+++ b/src/exercises/bare-metal/rtc/src/main.rs
@@ -23,11 +23,12 @@ mod pl011;
 // ANCHOR_END: top
 mod pl031;
 
-use crate::gicv3::{irq_enable, wfi, GicV3, IntId, Trigger};
+use crate::gicv3::{irq_enable, wfi, IntId, Trigger};
 use crate::pl031::Rtc;
 use chrono::{TimeZone, Utc};
 use core::hint::spin_loop;
 // ANCHOR: imports
+use crate::gicv3::GicV3;
 use crate::pl011::Uart;
 use core::panic::PanicInfo;
 use log::{error, info, trace, LevelFilter};
@@ -55,13 +56,13 @@ extern "C" fn main(x0: u64, x1: u64, x2: u64, x3: u64) {
     logger::init(uart, LevelFilter::Trace).unwrap();
 
     info!("main({:#x}, {:#x}, {:#x}, {:#x})", x0, x1, x2, x3);
-    // ANCHOR_END: main
 
     // Safe because `GICD_BASE_ADDRESS` and `GICR_BASE_ADDRESS` are the base
     // addresses of a GICv3 distributor and redistributor respectively, and
     // nothing else accesses those address ranges.
     let mut gic = unsafe { GicV3::new(GICD_BASE_ADDRESS, GICR_BASE_ADDRESS) };
     gic.setup();
+    // ANCHOR_END: main
 
     // Safe because `PL031_BASE_ADDRESS` is the base address of a PL031 device,
     // and nothing else accesses that address range.