From 5e0f4da4b3b19a4c3485eafd5ab4aa2e3424aafb Mon Sep 17 00:00:00 2001
From: Andrew Walbran <qwandor@google.com>
Date: Mon, 13 Feb 2023 03:12:58 +0000
Subject: [PATCH] Mention some other projects.

---
 src/SUMMARY.md                                |  1 +
 src/bare-metal/microcontrollers.md            |  4 ++++
 .../microcontrollers/other-projects.md        | 20 +++++++++++++++++++
 3 files changed, 25 insertions(+)
 create mode 100644 src/bare-metal/microcontrollers/other-projects.md

diff --git a/src/SUMMARY.md b/src/SUMMARY.md
index 0e802c4d..95c1a06b 100644
--- a/src/SUMMARY.md
+++ b/src/SUMMARY.md
@@ -244,6 +244,7 @@
   - [HAL crates](bare-metal/microcontrollers/hals.md)
   - [The type state pattern](bare-metal/microcontrollers/type-state.md)
   - [embedded-hal](bare-metal/microcontrollers/embedded-hal.md)
+  - [Other projects](bare-metal/microcontrollers/other-projects.md)
 
 # Day 5A: Afternoon
 
diff --git a/src/bare-metal/microcontrollers.md b/src/bare-metal/microcontrollers.md
index 342280ab..f81492ed 100644
--- a/src/bare-metal/microcontrollers.md
+++ b/src/bare-metal/microcontrollers.md
@@ -1 +1,5 @@
 # Microcontrollers
+
+ * Peripheral Access Crates
+ * HAL crates
+ * Other projects
diff --git a/src/bare-metal/microcontrollers/other-projects.md b/src/bare-metal/microcontrollers/other-projects.md
new file mode 100644
index 00000000..16db5193
--- /dev/null
+++ b/src/bare-metal/microcontrollers/other-projects.md
@@ -0,0 +1,20 @@
+# Other projects
+
+ * [RTIC](https://rtic.rs/)
+   * "Real-Time Interrupt-driven Concurrency"
+   * Shared resource management, message passing, task scheduling, timer queue
+ * [Embassy](https://embassy.dev/)
+   * `async` executors with priorities, timers, networking, USB
+ * [TockOS](https://www.tockos.org/documentation/getting-started)
+   * Security-focused RTOS with preemptive scheduling and Memory Protection Unit support
+ * Some platforms have `std` implementations, e.g. esp-idf.
+
+<details>
+
+ * RTIC can be considered either an RTOS or a concurrency framework.
+   * It doesn't include any HALs.
+   * It uses the Cortex-M NVIC (Nested Virtual Interrupt Controller) for scheduling rather than a
+     proper kernel.
+   * Cortex-M only.
+
+</details>