mirror of
https://github.com/google/comprehensive-rust.git
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Add RTC exercise.
This commit is contained in:
Andrew Walbran
parent
8b21f5070e
commit
fb3fd3979c
@ -276,6 +276,8 @@
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- [spin and once_cell]()
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- [Android]()
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- [vmbase]()
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- [Exercises](exercises/bare-metal/afternoon.md)
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- [RTC driver](exercises/bare-metal/rtc.md)
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---
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@ -292,3 +294,4 @@
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- [Day 3 Afternoon](exercises/day-3/solutions-afternoon.md)
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- [Day 4 Morning](exercises/day-4/solutions-morning.md)
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- [Bare Metal Rust Morning](exercises/bare-metal/solutions-morning.md)
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- [Bare Metal Rust Afternoon](exercises/bare-metal/solutions-afternoon.md)
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11
src/exercises/bare-metal/afternoon.md
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11
src/exercises/bare-metal/afternoon.md
Normal file
@ -0,0 +1,11 @@
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# Exercises
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We will write a driver for the PL031 real-time clock device.
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<details>
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After looking at the exercises, you can look at the [solutions] provided.
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[solutions]: solutions-afternoon.md
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</details>
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78
src/exercises/bare-metal/rtc.md
Normal file
78
src/exercises/bare-metal/rtc.md
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@ -0,0 +1,78 @@
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# RTC driver
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The QEMU aarch64 virt machine has a [PL031][1] real-time clock at 0x9010000. For this exercise, you
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should write a driver for it and use it to print the current time to the serial console. You can use
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the [`chrono`][2] crate for date/time formatting.
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`src/main.rs`:
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```rust,compile_fail
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{{#include rtc/src/main.rs:top}}
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{{#include rtc/src/main.rs:imports}}
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{{#include rtc/src/main.rs:main}}
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// TODO: Initialise RTC and print value.
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{{#include rtc/src/main.rs:main_end}}
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```
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`src/exceptions.rs` (you shouldn't need to change this):
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```rust,compile_fail
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{{#include rtc/src/exceptions.rs}}
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```
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`src/logger.rs` (you shouldn't need to change this):
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```rust,compile_fail
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{{#include rtc/src/logger.rs}}
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```
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`src/pl011.rs` (you shouldn't need to change this):
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```rust,compile_fail
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{{#include rtc/src/pl011.rs}}
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```
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`Cargo.toml` (you shouldn't need to change this):
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```toml
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{{#include rtc/Cargo.toml}}
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```
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`build.rs` (you shouldn't need to change this):
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```rust,compile_fail
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{{#include rtc/build.rs}}
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```
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`entry.S` (you shouldn't need to change this):
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```armasm
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{{#include rtc/entry.S}}
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```
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`exceptions.S` (you shouldn't need to change this):
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```armasm
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{{#include rtc/exceptions.S}}
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```
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`idmap.S` (you shouldn't need to change this):
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```armasm
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{{#include rtc/idmap.S}}
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```
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`image.ld` (you shouldn't need to change this):
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```ld
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{{#include rtc/image.ld}}
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```
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`Makefile` (you shouldn't need to change this):
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```makefile
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{{#include rtc/Makefile}}
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```
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`.cargo/config.toml` (you shouldn't need to change this):
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```toml
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{{#include rtc/.cargo/config.toml}}
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```
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Run the code in QEMU with `make qemu`.
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[1]: https://developer.arm.com/documentation/ddi0224/c
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[2]: https://crates.io/crates/chrono
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3
src/exercises/bare-metal/rtc/.cargo/config.toml
Normal file
3
src/exercises/bare-metal/rtc/.cargo/config.toml
Normal file
@ -0,0 +1,3 @@
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[build]
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target = "aarch64-unknown-none"
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rustflags = ["-C", "link-arg=-Timage.ld"]
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108
src/exercises/bare-metal/rtc/Cargo.lock
generated
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108
src/exercises/bare-metal/rtc/Cargo.lock
generated
Normal file
@ -0,0 +1,108 @@
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# This file is automatically @generated by Cargo.
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# It is not intended for manual editing.
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version = 3
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[[package]]
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name = "autocfg"
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version = "1.1.0"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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checksum = "d468802bab17cbc0cc575e9b053f41e72aa36bfa6b7f55e3529ffa43161b97fa"
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[[package]]
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name = "bitflags"
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version = "2.0.2"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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checksum = "487f1e0fcbe47deb8b0574e646def1c903389d95241dd1bbcc6ce4a715dfc0c1"
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[[package]]
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name = "cc"
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version = "1.0.79"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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checksum = "50d30906286121d95be3d479533b458f87493b30a4b5f79a607db8f5d11aa91f"
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[[package]]
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name = "cfg-if"
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version = "1.0.0"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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checksum = "baf1de4339761588bc0619e3cbc0120ee582ebb74b53b4efbf79117bd2da40fd"
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[[package]]
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name = "chrono"
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version = "0.4.24"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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checksum = "4e3c5919066adf22df73762e50cffcde3a758f2a848b113b586d1f86728b673b"
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dependencies = [
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"num-integer",
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"num-traits",
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]
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[[package]]
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name = "lock_api"
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version = "0.4.9"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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checksum = "435011366fe56583b16cf956f9df0095b405b82d76425bc8981c0e22e60ec4df"
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dependencies = [
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"autocfg",
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"scopeguard",
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]
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[[package]]
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name = "log"
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version = "0.4.17"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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checksum = "abb12e687cfb44aa40f41fc3978ef76448f9b6038cad6aef4259d3c095a2382e"
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dependencies = [
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"cfg-if",
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]
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[[package]]
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name = "num-integer"
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version = "0.1.45"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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checksum = "225d3389fb3509a24c93f5c29eb6bde2586b98d9f016636dff58d7c6f7569cd9"
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dependencies = [
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"autocfg",
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"num-traits",
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]
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[[package]]
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name = "num-traits"
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version = "0.2.15"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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checksum = "578ede34cf02f8924ab9447f50c28075b4d3e5b269972345e7e0372b38c6cdcd"
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dependencies = [
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"autocfg",
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]
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[[package]]
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name = "psci"
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version = "0.1.1"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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checksum = "3374e3ae47f134467227a48be93b929e5d304efcd25ce5d176006403ca1d9bab"
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[[package]]
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name = "rtc"
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version = "0.1.0"
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dependencies = [
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"bitflags",
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"cc",
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"chrono",
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"log",
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"psci",
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"spin",
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]
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[[package]]
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name = "scopeguard"
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version = "1.1.0"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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checksum = "d29ab0c6d3fc0ee92fe66e2d99f700eab17a8d57d1c1d3b748380fb20baa78cd"
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[[package]]
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name = "spin"
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version = "0.9.6"
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source = "registry+https://github.com/rust-lang/crates.io-index"
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checksum = "b5d6e0250b93c8427a177b849d144a96d5acc57006149479403d7861ab721e34"
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dependencies = [
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"lock_api",
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]
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16
src/exercises/bare-metal/rtc/Cargo.toml
Normal file
16
src/exercises/bare-metal/rtc/Cargo.toml
Normal file
@ -0,0 +1,16 @@
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[workspace]
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[package]
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name = "rtc"
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version = "0.1.0"
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edition = "2021"
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[dependencies]
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bitflags = "2.0.0"
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chrono = { version = "0.4.24", default-features = false }
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log = "0.4.17"
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psci = "0.1.1"
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spin = "0.9.4"
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[build-dependencies]
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cc = "1.0.73"
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30
src/exercises/bare-metal/rtc/Makefile
Normal file
30
src/exercises/bare-metal/rtc/Makefile
Normal file
@ -0,0 +1,30 @@
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# Copyright 2023 Google LLC
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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.PHONY: build qemu_minimal qemu qemu_logger
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all: rtc.bin
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build:
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cargo build
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rtc.bin: build
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aarch64-linux-gnu-objcopy -O binary target/aarch64-unknown-none/debug/rtc $@
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qemu: rtc.bin
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qemu-system-aarch64 -machine virt -cpu max -serial mon:stdio -display none -kernel $< -s
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clean:
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cargo clean
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rm -f *.bin
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25
src/exercises/bare-metal/rtc/build.rs
Normal file
25
src/exercises/bare-metal/rtc/build.rs
Normal file
@ -0,0 +1,25 @@
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// Copyright 2023 Google LLC
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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use cc::Build;
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use std::env;
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fn main() {
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env::set_var("CROSS_COMPILE", "aarch64-linux-gnu");
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Build::new()
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.file("entry.S")
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.file("exceptions.S")
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.file("idmap.S")
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.compile("empty")
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}
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142
src/exercises/bare-metal/rtc/entry.S
Normal file
142
src/exercises/bare-metal/rtc/entry.S
Normal file
@ -0,0 +1,142 @@
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/*
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* Copyright 2023 Google LLC
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* https://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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.macro adr_l, reg:req, sym:req
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adrp \reg, \sym
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add \reg, \reg, :lo12:\sym
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.endm
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.macro mov_i, reg:req, imm:req
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movz \reg, :abs_g3:\imm
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movk \reg, :abs_g2_nc:\imm
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movk \reg, :abs_g1_nc:\imm
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movk \reg, :abs_g0_nc:\imm
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.endm
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.set .L_MAIR_DEV_nGnRE, 0x04
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.set .L_MAIR_MEM_WBWA, 0xff
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.set .Lmairval, .L_MAIR_DEV_nGnRE | (.L_MAIR_MEM_WBWA << 8)
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/* 4 KiB granule size for TTBR0_EL1. */
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.set .L_TCR_TG0_4KB, 0x0 << 14
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/* 4 KiB granule size for TTBR1_EL1. */
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.set .L_TCR_TG1_4KB, 0x2 << 30
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/* Disable translation table walk for TTBR1_EL1, generating a translation fault instead. */
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.set .L_TCR_EPD1, 0x1 << 23
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/* Translation table walks for TTBR0_EL1 are inner sharable. */
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.set .L_TCR_SH_INNER, 0x3 << 12
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/*
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* Translation table walks for TTBR0_EL1 are outer write-back read-allocate write-allocate
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* cacheable.
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*/
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.set .L_TCR_RGN_OWB, 0x1 << 10
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/*
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* Translation table walks for TTBR0_EL1 are inner write-back read-allocate write-allocate
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* cacheable.
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*/
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.set .L_TCR_RGN_IWB, 0x1 << 8
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/* Size offset for TTBR0_EL1 is 2**39 bytes (512 GiB). */
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.set .L_TCR_T0SZ_512, 64 - 39
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.set .Ltcrval, .L_TCR_TG0_4KB | .L_TCR_TG1_4KB | .L_TCR_EPD1 | .L_TCR_RGN_OWB
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.set .Ltcrval, .Ltcrval | .L_TCR_RGN_IWB | .L_TCR_SH_INNER | .L_TCR_T0SZ_512
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/* Stage 1 instruction access cacheability is unaffected. */
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.set .L_SCTLR_ELx_I, 0x1 << 12
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/* SP alignment fault if SP is not aligned to a 16 byte boundary. */
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.set .L_SCTLR_ELx_SA, 0x1 << 3
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/* Stage 1 data access cacheability is unaffected. */
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.set .L_SCTLR_ELx_C, 0x1 << 2
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/* EL0 and EL1 stage 1 MMU enabled. */
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.set .L_SCTLR_ELx_M, 0x1 << 0
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/* Privileged Access Never is unchanged on taking an exception to EL1. */
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.set .L_SCTLR_EL1_SPAN, 0x1 << 23
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/* SETEND instruction disabled at EL0 in aarch32 mode. */
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.set .L_SCTLR_EL1_SED, 0x1 << 8
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/* Various IT instructions are disabled at EL0 in aarch32 mode. */
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.set .L_SCTLR_EL1_ITD, 0x1 << 7
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.set .L_SCTLR_EL1_RES1, (0x1 << 11) | (0x1 << 20) | (0x1 << 22) | (0x1 << 28) | (0x1 << 29)
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.set .Lsctlrval, .L_SCTLR_ELx_M | .L_SCTLR_ELx_C | .L_SCTLR_ELx_SA | .L_SCTLR_EL1_ITD | .L_SCTLR_EL1_SED
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||||
.set .Lsctlrval, .Lsctlrval | .L_SCTLR_ELx_I | .L_SCTLR_EL1_SPAN | .L_SCTLR_EL1_RES1
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||||
|
||||
/**
|
||||
* This is a generic entry point for an image. It carries out the operations required to prepare the
|
||||
* loaded image to be run. Specifically, it zeroes the bss section using registers x25 and above,
|
||||
* prepares the stack, enables floating point, and sets up the exception vector. It preserves x0-x3
|
||||
* for the Rust entry point, as these may contain boot parameters.
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||||
*/
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||||
.section .init.entry, "ax"
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.global entry
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||||
entry:
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/* Load and apply the memory management configuration, ready to enable MMU and caches. */
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||||
adrp x30, idmap
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msr ttbr0_el1, x30
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mov_i x30, .Lmairval
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msr mair_el1, x30
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mov_i x30, .Ltcrval
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/* Copy the supported PA range into TCR_EL1.IPS. */
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mrs x29, id_aa64mmfr0_el1
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bfi x30, x29, #32, #4
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msr tcr_el1, x30
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mov_i x30, .Lsctlrval
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/*
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||||
* Ensure everything before this point has completed, then invalidate any potentially stale
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||||
* local TLB entries before they start being used.
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||||
*/
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||||
isb
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||||
tlbi vmalle1
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||||
ic iallu
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||||
dsb nsh
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||||
isb
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||||
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/*
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||||
* Configure sctlr_el1 to enable MMU and cache and don't proceed until this has completed.
|
||||
*/
|
||||
msr sctlr_el1, x30
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||||
isb
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||||
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||||
/* Disable trapping floating point access in EL1. */
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||||
mrs x30, cpacr_el1
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||||
orr x30, x30, #(0x3 << 20)
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||||
msr cpacr_el1, x30
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isb
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||||
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||||
/* Zero out the bss section. */
|
||||
adr_l x29, bss_begin
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||||
adr_l x30, bss_end
|
||||
0: cmp x29, x30
|
||||
b.hs 1f
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||||
stp xzr, xzr, [x29], #16
|
||||
b 0b
|
||||
|
||||
1: /* Prepare the stack. */
|
||||
adr_l x30, boot_stack_end
|
||||
mov sp, x30
|
||||
|
||||
/* Set up exception vector. */
|
||||
adr x30, vector_table_el1
|
||||
msr vbar_el1, x30
|
||||
|
||||
/* Call into Rust code. */
|
||||
bl main
|
||||
|
||||
/* Loop forever waiting for interrupts. */
|
||||
2: wfi
|
||||
b 2b
|
||||
178
src/exercises/bare-metal/rtc/exceptions.S
Normal file
178
src/exercises/bare-metal/rtc/exceptions.S
Normal file
@ -0,0 +1,178 @@
|
||||
/*
|
||||
* Copyright 2023 Google LLC
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* https://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* Saves the volatile registers onto the stack. This currently takes 14
|
||||
* instructions, so it can be used in exception handlers with 18 instructions
|
||||
* left.
|
||||
*
|
||||
* On return, x0 and x1 are initialised to elr_el2 and spsr_el2 respectively,
|
||||
* which can be used as the first and second arguments of a subsequent call.
|
||||
*/
|
||||
.macro save_volatile_to_stack
|
||||
/* Reserve stack space and save registers x0-x18, x29 & x30. */
|
||||
stp x0, x1, [sp, #-(8 * 24)]!
|
||||
stp x2, x3, [sp, #8 * 2]
|
||||
stp x4, x5, [sp, #8 * 4]
|
||||
stp x6, x7, [sp, #8 * 6]
|
||||
stp x8, x9, [sp, #8 * 8]
|
||||
stp x10, x11, [sp, #8 * 10]
|
||||
stp x12, x13, [sp, #8 * 12]
|
||||
stp x14, x15, [sp, #8 * 14]
|
||||
stp x16, x17, [sp, #8 * 16]
|
||||
str x18, [sp, #8 * 18]
|
||||
stp x29, x30, [sp, #8 * 20]
|
||||
|
||||
/*
|
||||
* Save elr_el1 & spsr_el1. This such that we can take nested exception
|
||||
* and still be able to unwind.
|
||||
*/
|
||||
mrs x0, elr_el1
|
||||
mrs x1, spsr_el1
|
||||
stp x0, x1, [sp, #8 * 22]
|
||||
.endm
|
||||
|
||||
/**
|
||||
* Restores the volatile registers from the stack. This currently takes 14
|
||||
* instructions, so it can be used in exception handlers while still leaving 18
|
||||
* instructions left; if paired with save_volatile_to_stack, there are 4
|
||||
* instructions to spare.
|
||||
*/
|
||||
.macro restore_volatile_from_stack
|
||||
/* Restore registers x2-x18, x29 & x30. */
|
||||
ldp x2, x3, [sp, #8 * 2]
|
||||
ldp x4, x5, [sp, #8 * 4]
|
||||
ldp x6, x7, [sp, #8 * 6]
|
||||
ldp x8, x9, [sp, #8 * 8]
|
||||
ldp x10, x11, [sp, #8 * 10]
|
||||
ldp x12, x13, [sp, #8 * 12]
|
||||
ldp x14, x15, [sp, #8 * 14]
|
||||
ldp x16, x17, [sp, #8 * 16]
|
||||
ldr x18, [sp, #8 * 18]
|
||||
ldp x29, x30, [sp, #8 * 20]
|
||||
|
||||
/* Restore registers elr_el1 & spsr_el1, using x0 & x1 as scratch. */
|
||||
ldp x0, x1, [sp, #8 * 22]
|
||||
msr elr_el1, x0
|
||||
msr spsr_el1, x1
|
||||
|
||||
/* Restore x0 & x1, and release stack space. */
|
||||
ldp x0, x1, [sp], #8 * 24
|
||||
.endm
|
||||
|
||||
/**
|
||||
* This is a generic handler for exceptions taken at the current EL while using
|
||||
* SP0. It behaves similarly to the SPx case by first switching to SPx, doing
|
||||
* the work, then switching back to SP0 before returning.
|
||||
*
|
||||
* Switching to SPx and calling the Rust handler takes 16 instructions. To
|
||||
* restore and return we need an additional 16 instructions, so we can implement
|
||||
* the whole handler within the allotted 32 instructions.
|
||||
*/
|
||||
.macro current_exception_sp0 handler:req
|
||||
msr spsel, #1
|
||||
save_volatile_to_stack
|
||||
bl \handler
|
||||
restore_volatile_from_stack
|
||||
msr spsel, #0
|
||||
eret
|
||||
.endm
|
||||
|
||||
/**
|
||||
* This is a generic handler for exceptions taken at the current EL while using
|
||||
* SPx. It saves volatile registers, calls the Rust handler, restores volatile
|
||||
* registers, then returns.
|
||||
*
|
||||
* This also works for exceptions taken from EL0, if we don't care about
|
||||
* non-volatile registers.
|
||||
*
|
||||
* Saving state and jumping to the Rust handler takes 15 instructions, and
|
||||
* restoring and returning also takes 15 instructions, so we can fit the whole
|
||||
* handler in 30 instructions, under the limit of 32.
|
||||
*/
|
||||
.macro current_exception_spx handler:req
|
||||
save_volatile_to_stack
|
||||
bl \handler
|
||||
restore_volatile_from_stack
|
||||
eret
|
||||
.endm
|
||||
|
||||
.section .text.vector_table_el1, "ax"
|
||||
.global vector_table_el1
|
||||
.balign 0x800
|
||||
vector_table_el1:
|
||||
sync_cur_sp0:
|
||||
current_exception_sp0 sync_exception_current
|
||||
|
||||
.balign 0x80
|
||||
irq_cur_sp0:
|
||||
current_exception_sp0 irq_current
|
||||
|
||||
.balign 0x80
|
||||
fiq_cur_sp0:
|
||||
current_exception_sp0 fiq_current
|
||||
|
||||
.balign 0x80
|
||||
serr_cur_sp0:
|
||||
current_exception_sp0 serr_current
|
||||
|
||||
.balign 0x80
|
||||
sync_cur_spx:
|
||||
current_exception_spx sync_exception_current
|
||||
|
||||
.balign 0x80
|
||||
irq_cur_spx:
|
||||
current_exception_spx irq_current
|
||||
|
||||
.balign 0x80
|
||||
fiq_cur_spx:
|
||||
current_exception_spx fiq_current
|
||||
|
||||
.balign 0x80
|
||||
serr_cur_spx:
|
||||
current_exception_spx serr_current
|
||||
|
||||
.balign 0x80
|
||||
sync_lower_64:
|
||||
current_exception_spx sync_lower
|
||||
|
||||
.balign 0x80
|
||||
irq_lower_64:
|
||||
current_exception_spx irq_lower
|
||||
|
||||
.balign 0x80
|
||||
fiq_lower_64:
|
||||
current_exception_spx fiq_lower
|
||||
|
||||
.balign 0x80
|
||||
serr_lower_64:
|
||||
current_exception_spx serr_lower
|
||||
|
||||
.balign 0x80
|
||||
sync_lower_32:
|
||||
current_exception_spx sync_lower
|
||||
|
||||
.balign 0x80
|
||||
irq_lower_32:
|
||||
current_exception_spx irq_lower
|
||||
|
||||
.balign 0x80
|
||||
fiq_lower_32:
|
||||
current_exception_spx fiq_lower
|
||||
|
||||
.balign 0x80
|
||||
serr_lower_32:
|
||||
current_exception_spx serr_lower
|
||||
42
src/exercises/bare-metal/rtc/idmap.S
Normal file
42
src/exercises/bare-metal/rtc/idmap.S
Normal file
@ -0,0 +1,42 @@
|
||||
/*
|
||||
* Copyright 2023 Google LLC
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* https://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
.set .L_TT_TYPE_BLOCK, 0x1
|
||||
.set .L_TT_TYPE_PAGE, 0x3
|
||||
.set .L_TT_TYPE_TABLE, 0x3
|
||||
|
||||
/* Access flag. */
|
||||
.set .L_TT_AF, 0x1 << 10
|
||||
/* Not global. */
|
||||
.set .L_TT_NG, 0x1 << 11
|
||||
.set .L_TT_XN, 0x3 << 53
|
||||
|
||||
.set .L_TT_MT_DEV, 0x0 << 2 // MAIR #0 (DEV_nGnRE)
|
||||
.set .L_TT_MT_MEM, (0x1 << 2) | (0x3 << 8) // MAIR #1 (MEM_WBWA), inner shareable
|
||||
|
||||
.set .L_BLOCK_DEV, .L_TT_TYPE_BLOCK | .L_TT_MT_DEV | .L_TT_AF | .L_TT_XN
|
||||
.set .L_BLOCK_MEM, .L_TT_TYPE_BLOCK | .L_TT_MT_MEM | .L_TT_AF | .L_TT_NG
|
||||
|
||||
.section ".rodata.idmap", "a", %progbits
|
||||
.global idmap
|
||||
.align 12
|
||||
idmap:
|
||||
/* level 1 */
|
||||
.quad .L_BLOCK_DEV | 0x0 // 1 GiB of device mappings
|
||||
.quad .L_BLOCK_MEM | 0x40000000 // 1 GiB of DRAM
|
||||
.fill 254, 8, 0x0 // 254 GiB of unmapped VA space
|
||||
.quad .L_BLOCK_DEV | 0x4000000000 // 1 GiB of device mappings
|
||||
.fill 255, 8, 0x0 // 255 GiB of remaining VA space
|
||||
104
src/exercises/bare-metal/rtc/image.ld
Normal file
104
src/exercises/bare-metal/rtc/image.ld
Normal file
@ -0,0 +1,104 @@
|
||||
/*
|
||||
* Copyright 2023 Google LLC
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* https://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Code will start running at this symbol which is placed at the start of the
|
||||
* image.
|
||||
*/
|
||||
ENTRY(entry)
|
||||
|
||||
MEMORY
|
||||
{
|
||||
image : ORIGIN = 0x40080000, LENGTH = 2M
|
||||
}
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
/*
|
||||
* Collect together the code.
|
||||
*/
|
||||
.init : ALIGN(4096) {
|
||||
text_begin = .;
|
||||
*(.init.entry)
|
||||
*(.init.*)
|
||||
} >image
|
||||
.text : {
|
||||
*(.text.*)
|
||||
} >image
|
||||
text_end = .;
|
||||
|
||||
/*
|
||||
* Collect together read-only data.
|
||||
*/
|
||||
.rodata : ALIGN(4096) {
|
||||
rodata_begin = .;
|
||||
*(.rodata.*)
|
||||
} >image
|
||||
.got : {
|
||||
*(.got)
|
||||
} >image
|
||||
rodata_end = .;
|
||||
|
||||
/*
|
||||
* Collect together the read-write data including .bss at the end which
|
||||
* will be zero'd by the entry code.
|
||||
*/
|
||||
.data : ALIGN(4096) {
|
||||
data_begin = .;
|
||||
*(.data.*)
|
||||
/*
|
||||
* The entry point code assumes that .data is a multiple of 32
|
||||
* bytes long.
|
||||
*/
|
||||
. = ALIGN(32);
|
||||
data_end = .;
|
||||
} >image
|
||||
|
||||
/* Everything beyond this point will not be included in the binary. */
|
||||
bin_end = .;
|
||||
|
||||
/* The entry point code assumes that .bss is 16-byte aligned. */
|
||||
.bss : ALIGN(16) {
|
||||
bss_begin = .;
|
||||
*(.bss.*)
|
||||
*(COMMON)
|
||||
. = ALIGN(16);
|
||||
bss_end = .;
|
||||
} >image
|
||||
|
||||
.stack (NOLOAD) : ALIGN(4096) {
|
||||
boot_stack_begin = .;
|
||||
. += 40 * 4096;
|
||||
. = ALIGN(4096);
|
||||
boot_stack_end = .;
|
||||
} >image
|
||||
|
||||
. = ALIGN(4K);
|
||||
PROVIDE(dma_region = .);
|
||||
|
||||
/*
|
||||
* Remove unused sections from the image.
|
||||
*/
|
||||
/DISCARD/ : {
|
||||
/* The image loads itself so doesn't need these sections. */
|
||||
*(.gnu.hash)
|
||||
*(.hash)
|
||||
*(.interp)
|
||||
*(.eh_frame_hdr)
|
||||
*(.eh_frame)
|
||||
*(.note.gnu.build-id)
|
||||
}
|
||||
}
|
||||
64
src/exercises/bare-metal/rtc/src/exceptions.rs
Normal file
64
src/exercises/bare-metal/rtc/src/exceptions.rs
Normal file
@ -0,0 +1,64 @@
|
||||
// Copyright 2023 Google LLC
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
use log::error;
|
||||
use psci::system_off;
|
||||
|
||||
#[no_mangle]
|
||||
extern "C" fn sync_exception_current(_elr: u64, _spsr: u64) {
|
||||
error!("sync_exception_current");
|
||||
system_off().unwrap();
|
||||
}
|
||||
|
||||
#[no_mangle]
|
||||
extern "C" fn irq_current(_elr: u64, _spsr: u64) {
|
||||
error!("irq_current");
|
||||
system_off().unwrap();
|
||||
}
|
||||
|
||||
#[no_mangle]
|
||||
extern "C" fn fiq_current(_elr: u64, _spsr: u64) {
|
||||
error!("fiq_current");
|
||||
system_off().unwrap();
|
||||
}
|
||||
|
||||
#[no_mangle]
|
||||
extern "C" fn serr_current(_elr: u64, _spsr: u64) {
|
||||
error!("serr_current");
|
||||
system_off().unwrap();
|
||||
}
|
||||
|
||||
#[no_mangle]
|
||||
extern "C" fn sync_lower(_elr: u64, _spsr: u64) {
|
||||
error!("sync_lower");
|
||||
system_off().unwrap();
|
||||
}
|
||||
|
||||
#[no_mangle]
|
||||
extern "C" fn irq_lower(_elr: u64, _spsr: u64) {
|
||||
error!("irq_lower");
|
||||
system_off().unwrap();
|
||||
}
|
||||
|
||||
#[no_mangle]
|
||||
extern "C" fn fiq_lower(_elr: u64, _spsr: u64) {
|
||||
error!("fiq_lower");
|
||||
system_off().unwrap();
|
||||
}
|
||||
|
||||
#[no_mangle]
|
||||
extern "C" fn serr_lower(_elr: u64, _spsr: u64) {
|
||||
error!("serr_lower");
|
||||
system_off().unwrap();
|
||||
}
|
||||
54
src/exercises/bare-metal/rtc/src/logger.rs
Normal file
54
src/exercises/bare-metal/rtc/src/logger.rs
Normal file
@ -0,0 +1,54 @@
|
||||
// Copyright 2023 Google LLC
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
// ANCHOR: main
|
||||
use crate::pl011::Uart;
|
||||
use core::fmt::Write;
|
||||
use log::{LevelFilter, Log, Metadata, Record, SetLoggerError};
|
||||
use spin::mutex::SpinMutex;
|
||||
|
||||
static LOGGER: Logger = Logger {
|
||||
uart: SpinMutex::new(None),
|
||||
};
|
||||
|
||||
struct Logger {
|
||||
uart: SpinMutex<Option<Uart>>,
|
||||
}
|
||||
|
||||
impl Log for Logger {
|
||||
fn enabled(&self, _metadata: &Metadata) -> bool {
|
||||
true
|
||||
}
|
||||
|
||||
fn log(&self, record: &Record) {
|
||||
writeln!(
|
||||
self.uart.lock().as_mut().unwrap(),
|
||||
"[{}] {}",
|
||||
record.level(),
|
||||
record.args()
|
||||
)
|
||||
.unwrap();
|
||||
}
|
||||
|
||||
fn flush(&self) {}
|
||||
}
|
||||
|
||||
/// Initialises UART logger.
|
||||
pub fn init(uart: Uart, max_level: LevelFilter) -> Result<(), SetLoggerError> {
|
||||
LOGGER.uart.lock().replace(uart);
|
||||
|
||||
log::set_logger(&LOGGER)?;
|
||||
log::set_max_level(max_level);
|
||||
Ok(())
|
||||
}
|
||||
67
src/exercises/bare-metal/rtc/src/main.rs
Normal file
67
src/exercises/bare-metal/rtc/src/main.rs
Normal file
@ -0,0 +1,67 @@
|
||||
// Copyright 2023 Google LLC
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
// ANCHOR: top
|
||||
#![no_main]
|
||||
#![no_std]
|
||||
|
||||
mod exceptions;
|
||||
mod logger;
|
||||
mod pl011;
|
||||
// ANCHOR_END: top
|
||||
mod pl031;
|
||||
|
||||
use crate::pl031::Rtc;
|
||||
use chrono::{TimeZone, Utc};
|
||||
// ANCHOR: imports
|
||||
use crate::pl011::Uart;
|
||||
use core::panic::PanicInfo;
|
||||
use log::{error, info, LevelFilter};
|
||||
use psci::system_off;
|
||||
|
||||
/// Base address of the primary PL011 UART.
|
||||
pub const PL011_BASE_ADDRESS: usize = 0x900_0000;
|
||||
// ANCHOR_END: imports
|
||||
|
||||
/// Base address of the PL031 RTC.
|
||||
pub const PL031_BASE_ADDRESS: usize = 0x901_0000;
|
||||
|
||||
// ANCHOR: main
|
||||
#[no_mangle]
|
||||
extern "C" fn main(x0: u64, x1: u64, x2: u64, x3: u64) {
|
||||
// Safe because `PL011_BASE_ADDRESS` is the base address of a PL011 device,
|
||||
// and nothing else accesses that address range.
|
||||
let uart = unsafe { Uart::new(PL011_BASE_ADDRESS as *mut u32) };
|
||||
logger::init(uart, LevelFilter::Trace).unwrap();
|
||||
|
||||
info!("main({:#x}, {:#x}, {:#x}, {:#x})", x0, x1, x2, x3);
|
||||
// ANCHOR_END: main
|
||||
|
||||
// Safe because `PL031_BASE_ADDRESS` is the base address of a PL031 device,
|
||||
// and nothing else accesses that address range.
|
||||
let rtc = unsafe { Rtc::new(PL031_BASE_ADDRESS as *mut u32) };
|
||||
let time = Utc.timestamp_opt(rtc.read().into(), 0).unwrap();
|
||||
info!("RTC: {}", time);
|
||||
|
||||
// ANCHOR: main_end
|
||||
system_off().unwrap();
|
||||
}
|
||||
|
||||
#[panic_handler]
|
||||
fn panic(info: &PanicInfo) -> ! {
|
||||
error!("{}", info);
|
||||
system_off().unwrap();
|
||||
loop {}
|
||||
}
|
||||
// ANCHOR_END: main_end
|
||||
168
src/exercises/bare-metal/rtc/src/pl011.rs
Normal file
168
src/exercises/bare-metal/rtc/src/pl011.rs
Normal file
@ -0,0 +1,168 @@
|
||||
// Copyright 2023 Google LLC
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
use core::{
|
||||
fmt::{self, Write},
|
||||
ptr::{addr_of, addr_of_mut},
|
||||
};
|
||||
|
||||
// ANCHOR: Flags
|
||||
use bitflags::bitflags;
|
||||
|
||||
bitflags! {
|
||||
/// Flags from the UART flag register.
|
||||
#[repr(transparent)]
|
||||
#[derive(Copy, Clone, Debug, Eq, PartialEq)]
|
||||
struct Flags: u16 {
|
||||
/// Clear to send.
|
||||
const CTS = 1 << 0;
|
||||
/// Data set ready.
|
||||
const DSR = 1 << 1;
|
||||
/// Data carrier detect.
|
||||
const DCD = 1 << 2;
|
||||
/// UART busy transmitting data.
|
||||
const BUSY = 1 << 3;
|
||||
/// Receive FIFO is empty.
|
||||
const RXFE = 1 << 4;
|
||||
/// Transmit FIFO is full.
|
||||
const TXFF = 1 << 5;
|
||||
/// Receive FIFO is full.
|
||||
const RXFF = 1 << 6;
|
||||
/// Transmit FIFO is empty.
|
||||
const TXFE = 1 << 7;
|
||||
/// Ring indicator.
|
||||
const RI = 1 << 8;
|
||||
}
|
||||
}
|
||||
// ANCHOR_END: Flags
|
||||
|
||||
bitflags! {
|
||||
/// Flags from the UART Receive Status Register / Error Clear Register.
|
||||
#[repr(transparent)]
|
||||
#[derive(Copy, Clone, Debug, Eq, PartialEq)]
|
||||
struct ReceiveStatus: u16 {
|
||||
/// Framing error.
|
||||
const FE = 1 << 0;
|
||||
/// Parity error.
|
||||
const PE = 1 << 1;
|
||||
/// Break error.
|
||||
const BE = 1 << 2;
|
||||
/// Overrun error.
|
||||
const OE = 1 << 3;
|
||||
}
|
||||
}
|
||||
|
||||
// ANCHOR: Registers
|
||||
#[repr(C, align(4))]
|
||||
struct Registers {
|
||||
dr: u16,
|
||||
_reserved0: [u8; 2],
|
||||
rsr: ReceiveStatus,
|
||||
_reserved1: [u8; 19],
|
||||
fr: Flags,
|
||||
_reserved2: [u8; 6],
|
||||
ilpr: u8,
|
||||
_reserved3: [u8; 3],
|
||||
ibrd: u16,
|
||||
_reserved4: [u8; 2],
|
||||
fbrd: u8,
|
||||
_reserved5: [u8; 3],
|
||||
lcr_h: u8,
|
||||
_reserved6: [u8; 3],
|
||||
cr: u16,
|
||||
_reserved7: [u8; 3],
|
||||
ifls: u8,
|
||||
_reserved8: [u8; 3],
|
||||
imsc: u16,
|
||||
_reserved9: [u8; 2],
|
||||
ris: u16,
|
||||
_reserved10: [u8; 2],
|
||||
mis: u16,
|
||||
_reserved11: [u8; 2],
|
||||
icr: u16,
|
||||
_reserved12: [u8; 2],
|
||||
dmacr: u8,
|
||||
_reserved13: [u8; 3],
|
||||
}
|
||||
// ANCHOR_END: Registers
|
||||
|
||||
// ANCHOR: Uart
|
||||
/// Driver for a PL011 UART.
|
||||
#[derive(Debug)]
|
||||
pub struct Uart {
|
||||
registers: *mut Registers,
|
||||
}
|
||||
|
||||
impl Uart {
|
||||
/// Constructs a new instance of the UART driver for a PL011 device at the
|
||||
/// given base address.
|
||||
///
|
||||
/// # Safety
|
||||
///
|
||||
/// The given base address must point to the MMIO control registers of a
|
||||
/// PL011 device, which must be mapped into the address space of the process
|
||||
/// as device memory and not have any other aliases.
|
||||
pub unsafe fn new(base_address: *mut u32) -> Self {
|
||||
Self {
|
||||
registers: base_address as *mut Registers,
|
||||
}
|
||||
}
|
||||
|
||||
/// Writes a single byte to the UART.
|
||||
pub fn write_byte(&self, byte: u8) {
|
||||
// Wait until there is room in the TX buffer.
|
||||
while self.read_flag_register().contains(Flags::TXFF) {}
|
||||
|
||||
// Safe because we know that self.registers points to the control
|
||||
// registers of a PL011 device which is appropriately mapped.
|
||||
unsafe {
|
||||
// Write to the TX buffer.
|
||||
addr_of_mut!((*self.registers).dr).write_volatile(byte.into());
|
||||
}
|
||||
|
||||
// Wait until the UART is no longer busy.
|
||||
while self.read_flag_register().contains(Flags::BUSY) {}
|
||||
}
|
||||
|
||||
/// Reads and returns a pending byte, or `None` if nothing has been received.
|
||||
pub fn read_byte(&self) -> Option<u8> {
|
||||
if self.read_flag_register().contains(Flags::RXFE) {
|
||||
None
|
||||
} else {
|
||||
let data = unsafe { addr_of!((*self.registers).dr).read_volatile() };
|
||||
// TODO: Check for error conditions in bits 8-11.
|
||||
Some(data as u8)
|
||||
}
|
||||
}
|
||||
|
||||
fn read_flag_register(&self) -> Flags {
|
||||
// Safe because we know that self.registers points to the control
|
||||
// registers of a PL011 device which is appropriately mapped.
|
||||
unsafe { addr_of!((*self.registers).fr).read_volatile() }
|
||||
}
|
||||
}
|
||||
// ANCHOR_END: Uart
|
||||
|
||||
impl Write for Uart {
|
||||
fn write_str(&mut self, s: &str) -> fmt::Result {
|
||||
for c in s.as_bytes() {
|
||||
self.write_byte(*c);
|
||||
}
|
||||
Ok(())
|
||||
}
|
||||
}
|
||||
|
||||
// Safe because it just contains a pointer to device memory, which can be
|
||||
// accessed from any context.
|
||||
unsafe impl Send for Uart {}
|
||||
70
src/exercises/bare-metal/rtc/src/pl031.rs
Normal file
70
src/exercises/bare-metal/rtc/src/pl031.rs
Normal file
@ -0,0 +1,70 @@
|
||||
// Copyright 2023 Google LLC
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
use core::ptr::addr_of;
|
||||
|
||||
#[repr(C, align(4))]
|
||||
struct Registers {
|
||||
/// Data register
|
||||
dr: u32,
|
||||
/// Match register
|
||||
mr: u32,
|
||||
/// Load register
|
||||
lr: u32,
|
||||
/// Control register
|
||||
cr: u8,
|
||||
_reserved0: [u8; 3],
|
||||
/// Interrupt Mask Set or Clear register
|
||||
imsc: u8,
|
||||
_reserved1: [u8; 3],
|
||||
/// Raw Interrupt Status
|
||||
ris: u8,
|
||||
_reserved2: [u8; 3],
|
||||
/// Masked Interrupt Status
|
||||
mis: u8,
|
||||
_reserved3: [u8; 3],
|
||||
/// Interrupt Clear Register
|
||||
icr: u8,
|
||||
_reserved4: [u8; 3],
|
||||
}
|
||||
|
||||
#[derive(Debug)]
|
||||
pub struct Rtc {
|
||||
registers: *mut Registers,
|
||||
}
|
||||
|
||||
impl Rtc {
|
||||
/// Constructs a new instance of the RTC driver for a PL031 device at the
|
||||
/// given base address.
|
||||
///
|
||||
/// # Safety
|
||||
///
|
||||
/// The given base address must point to the MMIO control registers of a
|
||||
/// PL031 device, which must be mapped into the address space of the process
|
||||
/// as device memory and not have any other aliases.
|
||||
pub unsafe fn new(base_address: *mut u32) -> Self {
|
||||
Self {
|
||||
registers: base_address as *mut Registers,
|
||||
}
|
||||
}
|
||||
|
||||
/// Reads the current RTC value.
|
||||
pub fn read(&self) -> u32 {
|
||||
unsafe { addr_of!((*self.registers).dr).read_volatile() }
|
||||
}
|
||||
}
|
||||
|
||||
// Safe because it just contains a pointer to device memory, which can be
|
||||
// accessed from any context.
|
||||
unsafe impl Send for Rtc {}
|
||||
9
src/exercises/bare-metal/solutions-afternoon.md
Normal file
9
src/exercises/bare-metal/solutions-afternoon.md
Normal file
@ -0,0 +1,9 @@
|
||||
# Bare Metal Rust Afternoon
|
||||
|
||||
## RTC driver
|
||||
|
||||
([back to exercise](rtc.md))
|
||||
|
||||
```rust,compile_fail
|
||||
{{#include rtc/src/main.rs}}
|
||||
```
|
||||
Loading…
x
Reference in New Issue
Block a user