\n"
" \n"
"* É por isso que é comum implementar apenas `From`, já que seu tipo também receberá a "
"implementação de `Into`.\n"
"* Ao declarar um tipo de entrada de argumento de função como \"qualquer coisa que possa ser "
"convertida em `String`\", a regra é oposta, você deve usar `Into`.\n"
" Sua função aceitará tipos que implementam `From` e aqueles que _apenas_ implementam `Into`.\n"
" \n"
"
"
#: src/traits/read-write.md:1
msgid "# `Read` and `Write`"
msgstr "# `Read` e `Write`"
#: src/traits/read-write.md:3
msgid "Using [`Read`][1] and [`BufRead`][2], you can abstract over `u8` sources:"
msgstr "Usando `Read` e `BufRead`, você pode abstrair a leitura de conteúdos do tipo `u8`:"
#: src/traits/read-write.md:5
msgid ""
"```rust,editable\n"
"use std::io::{BufRead, BufReader, Read, Result};\n"
"\n"
"fn count_lines![](\"cpp/overview.svg\")
"
msgstr ""
#: src/android/interoperability/cpp.md:10
msgid "See the [CXX tutorial][2] for an full example of using this."
msgstr "Veja o [tutorial CXX][2] para um exemplo completo de como usá-lo."
#: src/android/interoperability/java.md:1
msgid "# Interoperability with Java"
msgstr "# Interoperabilidade com Java"
#: src/android/interoperability/java.md:3
msgid ""
"Java can load shared objects via [Java Native Interface\n"
"(JNI)](https://en.wikipedia.org/wiki/Java_Native_Interface). The [`jni`\n"
"crate](https://docs.rs/jni/) allows you to create a compatible library."
msgstr ""
"Java pode carregar objetos compartilhados via [Java Native Interface\n"
"(JNI)](https://en.wikipedia.org/wiki/Java_Native_Interface).\n"
"O [crate `jni`](https://docs.rs/jni/) permite que você crie uma biblioteca compatível."
#: src/android/interoperability/java.md:7
msgid "First, we create a Rust function to export to Java:"
msgstr "Primeiro, criamos uma função Rust para exportar para Java:"
#: src/android/interoperability/java.md:9
msgid "_interoperability/java/src/lib.rs_:"
msgstr "_interoperability/java/src/lib.rs_:"
#: src/android/interoperability/java.md:11
#, fuzzy
msgid ""
"```rust,compile_fail\n"
"//! Rust <-> Java FFI demo.\n"
"\n"
"use jni::objects::{JClass, JString};\n"
"use jni::sys::jstring;\n"
"use jni::JNIEnv;\n"
"\n"
"/// HelloWorld::hello method implementation.\n"
"#[no_mangle]\n"
"pub extern \"system\" fn Java_HelloWorld_hello(\n"
" env: JNIEnv,\n"
" _class: JClass,\n"
" name: JString,\n"
") -> jstring {\n"
" let input: String = env.get_string(name).unwrap().into();\n"
" let greeting = format!(\"Hello, {input}!\");\n"
" let output = env.new_string(greeting).unwrap();\n"
" output.into_inner()\n"
"}\n"
"```"
msgstr ""
"/// Implementação do método HelloWorld::hello.\n"
"#[no_mangle]\n"
"pub extern \"system\" fn Java_HelloWorld_hello(\n"
" env: JNIEnv,\n"
" _class: JClass,\n"
" name: JString,\n"
") -> jstring {\n"
" let input: String = env.get_string(name).unwrap().into();\n"
" let greeting = format!(\"Olá, {input}!\");\n"
" let output = env.new_string(greeting).unwrap();\n"
" output.into_inner()\n"
"}\n"
"```"
#: src/android/interoperability/java.md:32 src/android/interoperability/java.md:62
msgid "_interoperability/java/Android.bp_:"
msgstr "_interoperability/java/Android.bp_:"
#: src/android/interoperability/java.md:34
msgid ""
"```javascript\n"
"rust_ffi_shared {\n"
" name: \"libhello_jni\",\n"
" crate_name: \"hello_jni\",\n"
" srcs: [\"src/lib.rs\"],\n"
" rustlibs: [\"libjni\"],\n"
"}\n"
"```"
msgstr ""
"```javascript\n"
"rust_ffi_shared {\n"
" name: \"libhello_jni\",\n"
" crate_name: \"hello_jni\",\n"
" srcs: [\"src/lib.rs\"],\n"
" rustlibs: [\"libjni\"],\n"
"}\n"
"```"
#: src/android/interoperability/java.md:43
msgid "Finally, we can call this function from Java:"
msgstr "Finalmente, podemos chamar esta função do Java:"
#: src/android/interoperability/java.md:45
msgid "_interoperability/java/HelloWorld.java_:"
msgstr "_interoperability/java/HelloWorld.java_:"
#: src/android/interoperability/java.md:47
#, fuzzy
msgid ""
"```java\n"
"class HelloWorld {\n"
" private static native String hello(String name);\n"
"\n"
" static {\n"
" System.loadLibrary(\"hello_jni\");\n"
" }\n"
"\n"
" public static void main(String[] args) {\n"
" String output = HelloWorld.hello(\"Alice\");\n"
" System.out.println(output);\n"
" }\n"
"}\n"
"```"
msgstr ""
" public static void main(String[] args) {\n"
" String output = HelloWorld.hello(\"Alice\");\n"
" System.out.println(output);\n"
" }\n"
"}\n"
"```"
#: src/android/interoperability/java.md:64
msgid ""
"```javascript\n"
"java_binary {\n"
" name: \"helloworld_jni\",\n"
" srcs: [\"HelloWorld.java\"],\n"
" main_class: \"HelloWorld\",\n"
" required: [\"libhello_jni\"],\n"
"}\n"
"```"
msgstr ""
"```javascript\n"
"java_binary {\n"
" name: \"helloworld_jni\",\n"
" srcs: [\"HelloWorld.java\"],\n"
" main_class: \"HelloWorld\",\n"
" necessário: [\"libhello_jni\"],\n"
"}\n"
"```"
#: src/android/interoperability/java.md:73
msgid "Finally, you can build, sync, and run the binary:"
msgstr "Por fim, você pode criar, sincronizar e executar o binário:"
#: src/android/interoperability/java.md:75
msgid ""
"```shell\n"
"$ m helloworld_jni\n"
"$ adb sync # requires adb root && adb remount\n"
"$ adb shell /system/bin/helloworld_jni\n"
"```"
msgstr ""
"```shell\n"
"$ m helloworld_jni\n"
"$ adb sync # requer adb root && adb remount\n"
"$ adb shell /system/bin/helloworld_jni\n"
"```"
#: src/exercises/android/morning.md:1 src/exercises/bare-metal/morning.md:1
#: src/exercises/bare-metal/afternoon.md:1 src/exercises/concurrency/morning.md:1
#: src/exercises/concurrency/afternoon.md:1
msgid "# Exercises"
msgstr "# Exercícios"
#: src/exercises/android/morning.md:3
#, fuzzy
msgid ""
"This is a group exercise: We will look at one of the projects you work with and\n"
"try to integrate some Rust into it. Some suggestions:"
msgstr ""
"No último exercício, veremos um dos projetos com os quais você trabalha. Chamem-nos\n"
"agrupem-se e façam isso juntos. Algumas sugestões:"
#: src/exercises/android/morning.md:6
#, fuzzy
msgid ""
"* Call your AIDL service with a client written in Rust.\n"
"\n"
"* Move a function from your project to Rust and call it."
msgstr "* Mova uma função do seu projeto para o Rust e chame-a."
#: src/exercises/android/morning.md:12
msgid ""
"No solution is provided here since this is open-ended: it relies on someone in\n"
"the class having a piece of code which you can turn in to Rust on the fly."
msgstr ""
"Nenhuma solução é fornecida aqui, pois isso é aberto: depende de você ter\n"
"uma classe tendo um pedaço de código que você pode transformar em Rust em tempo real."
#: src/bare-metal.md:1
#, fuzzy
msgid "# Welcome to Bare Metal Rust"
msgstr "# Bem-vindo ao Comprehensive Rust 🦀"
#: src/bare-metal.md:3
msgid ""
"This is a standalone one-day course about bare-metal Rust, aimed at people who are familiar with "
"the\n"
"basics of Rust (perhaps from completing the Comprehensive Rust course), and ideally also have "
"some\n"
"experience with bare-metal programming in some other language such as C."
msgstr ""
#: src/bare-metal.md:7
msgid ""
"Today we will talk about 'bare-metal' Rust: running Rust code without an OS underneath us. This "
"will\n"
"be divided into several parts:"
msgstr ""
#: src/bare-metal.md:10
msgid ""
"- What is `no_std` Rust?\n"
"- Writing firmware for microcontrollers.\n"
"- Writing bootloader / kernel code for application processors.\n"
"- Some useful crates for bare-metal Rust development."
msgstr ""
#: src/bare-metal.md:15
msgid ""
"For the microcontroller part of the course we will use the [BBC micro:bit](https://microbit.org/) "
"v2\n"
"as an example. It's a [development board](https://tech.microbit.org/hardware/) based on the "
"Nordic\n"
"nRF51822 microcontroller with some LEDs and buttons, an I2C-connected accelerometer and compass, "
"and\n"
"an on-board SWD debugger."
msgstr ""
#: src/bare-metal.md:20
msgid "To get started, install some tools we'll need later. On gLinux or Debian:"
msgstr ""
#: src/bare-metal.md:22
msgid ""
"```bash\n"
"sudo apt install gcc-aarch64-linux-gnu gdb-multiarch libudev-dev picocom pkg-config qemu-system-"
"arm\n"
"rustup update\n"
"rustup target add aarch64-unknown-none thumbv7em-none-eabihf\n"
"rustup component add llvm-tools-preview\n"
"cargo install cargo-binutils cargo-embed\n"
"```"
msgstr ""
#: src/bare-metal.md:30
msgid "And give users in the `plugdev` group access to the micro:bit programmer:"
msgstr ""
#: src/bare-metal.md:32
msgid ""
"```bash\n"
"echo 'SUBSYSTEM==\"usb\", ATTR{idVendor}==\"0d28\", MODE=\"0664\", GROUP=\"plugdev\"' |\\\n"
" sudo tee /etc/udev/rules.d/50-microbit.rules\n"
"sudo udevadm control --reload-rules\n"
"```"
msgstr ""
#: src/bare-metal.md:38
msgid "On MacOS:"
msgstr ""
#: src/bare-metal.md:40
msgid ""
"```bash\n"
"xcode-select --install\n"
"brew install gdb picocom qemu\n"
"brew install --cask gcc-aarch64-embedded\n"
"rustup update\n"
"rustup target add aarch64-unknown-none thumbv7em-none-eabihf\n"
"rustup component add llvm-tools-preview\n"
"cargo install cargo-binutils cargo-embed\n"
"```"
msgstr ""
#: src/bare-metal/no_std.md:1
msgid "# `no_std`"
msgstr ""
#: src/bare-metal/no_std.md:3
msgid ""
"| " msgstr "" #: src/bare-metal/no_std.md:7 msgid "`core`" msgstr "" #: src/bare-metal/no_std.md:9 src/bare-metal/no_std.md:14 msgid "" " | \n" "" msgstr "" #: src/bare-metal/no_std.md:12 msgid "`alloc`" msgstr "" #: src/bare-metal/no_std.md:17 msgid "`std`" msgstr "" #: src/bare-metal/no_std.md:19 msgid "" " | \n" "
|---|---|
| " msgstr "" #: src/bare-metal/no_std.md:24 msgid "" "* Slices, `&str`, `CStr`\n" "* `NonZeroU8`...\n" "* `Option`, `Result`\n" "* `Display`, `Debug`, `write!`...\n" "* `Iterator`\n" "* `panic!`, `assert_eq!`...\n" "* `NonNull` and all the usual pointer-related functions\n" "* `Future` and `async`/`await`\n" "* `fence`, `AtomicBool`, `AtomicPtr`, `AtomicU32`...\n" "* `Duration`" msgstr "" #: src/bare-metal/no_std.md:35 src/bare-metal/no_std.md:42 msgid "" " | \n" "" msgstr "" #: src/bare-metal/no_std.md:38 msgid "" "* `Box`, `Cow`, `Arc`, `Rc`\n" "* `Vec`, `BinaryHeap`, `BtreeMap`, `LinkedList`, `VecDeque`\n" "* `String`, `CString`, `format!`" msgstr "" #: src/bare-metal/no_std.md:45 msgid "" "* `Error`\n" "* `HashMap`\n" "* `Mutex`, `Condvar`, `Barrier`, `Once`, `RwLock`, `mpsc`\n" "* `File` and the rest of `fs`\n" "* `println!`, `Read`, `Write`, `Stdin`, `Stdout` and the rest of `io`\n" "* `Path`, `OsString`\n" "* `net`\n" "* `Command`, `Child`, `ExitCode`\n" "* `spawn`, `sleep` and the rest of `thread`\n" "* `SystemTime`, `Instant`" msgstr "" #: src/bare-metal/no_std.md:56 msgid "" " | \n" "
"
msgstr ""
#: src/bare-metal/no_std.md:62
msgid ""
"* `HashMap` depends on RNG.\n"
"* `std` re-exports the contents of both `core` and `alloc`."
msgstr ""
#: src/bare-metal/minimal.md:1
msgid "# A minimal `no_std` program"
msgstr ""
#: src/bare-metal/minimal.md:3
msgid ""
"```rust,editable,compile_fail\n"
"#![no_main]\n"
"#![no_std]\n"
"\n"
"use core::panic::PanicInfo;\n"
"\n"
"#[panic_handler]\n"
"fn panic(_panic: &PanicInfo) -> ! {\n"
" loop {}\n"
"}\n"
"```"
msgstr ""
#: src/bare-metal/minimal.md:17
msgid ""
"* This will compile to an empty binary.\n"
"* `std` provides a panic handler; without it we must provide our own.\n"
"* It can also be provided by another crate, such as `panic-halt`.\n"
"* Depending on the target, you may need to compile with `panic = \"abort\"` to avoid an error "
"about\n"
" `eh_personality`.\n"
"* Note that there is no `main` or any other entry point; it's up to you to define your own entry\n"
" point. This will typically involve a linker script and some assembly code to set things up "
"ready\n"
" for Rust code to run."
msgstr ""
#: src/bare-metal/alloc.md:1
msgid "# `alloc`"
msgstr ""
#: src/bare-metal/alloc.md:3
msgid ""
"To use `alloc` you must implement a\n"
"[global (heap) allocator](https://doc.rust-lang.org/stable/std/alloc/trait.GlobalAlloc.html)."
msgstr ""
#: src/bare-metal/alloc.md:6
msgid ""
"```rust,editable,compile_fail\n"
"#![no_main]\n"
"#![no_std]\n"
"\n"
"extern crate alloc;\n"
"extern crate panic_halt as _;\n"
"\n"
"use alloc::string::ToString;\n"
"use alloc::vec::Vec;\n"
"use buddy_system_allocator::LockedHeap;\n"
"\n"
"#[global_allocator]\n"
"static HEAP_ALLOCATOR: LockedHeap<32> = LockedHeap::<32>::new();\n"
"\n"
"static mut HEAP: [u8; 65536] = [0; 65536];\n"
"\n"
"pub fn entry() {\n"
" // Safe because `HEAP` is only used here and `entry` is only called once.\n"
" unsafe {\n"
" // Give the allocator some memory to allocate.\n"
" HEAP_ALLOCATOR\n"
" .lock()\n"
" .init(HEAP.as_mut_ptr() as usize, HEAP.len());\n"
" }\n"
"\n"
" // Now we can do things that require heap allocation.\n"
" let mut v = Vec::new();\n"
" v.push(\"A string\".to_string());\n"
"}\n"
"```"
msgstr ""
#: src/bare-metal/alloc.md:39
msgid ""
"* `buddy_system_allocator` is a third-party crate implementing a basic buddy system allocator. "
"Other\n"
" crates are available, or you can write your own or hook into your existing allocator.\n"
"* The const parameter of `LockedHeap` is the max order of the allocator; i.e. in this case it can\n"
" allocate regions of up to 2**32 bytes.\n"
"* If any crate in your dependency tree depends on `alloc` then you must have exactly one global\n"
" allocator defined in your binary. Usually this is done in the top-level binary crate.\n"
"* `extern crate panic_halt as _` is necessary to ensure that the `panic_halt` crate is linked in "
"so\n"
" we get its panic handler.\n"
"* This example will build but not run, as it doesn't have an entry point."
msgstr ""
#: src/bare-metal/microcontrollers.md:1
msgid "# Microcontrollers"
msgstr ""
#: src/bare-metal/microcontrollers.md:3
msgid ""
"The `cortex_m_rt` crate provides (among other things) a reset handler for Cortex M "
"microcontrollers."
msgstr ""
#: src/bare-metal/microcontrollers.md:5
msgid ""
"```rust,editable,compile_fail\n"
"#![no_main]\n"
"#![no_std]\n"
"\n"
"extern crate panic_halt as _;\n"
"\n"
"mod interrupts;\n"
"\n"
"use cortex_m_rt::entry;\n"
"\n"
"#[entry]\n"
"fn main() -> ! {\n"
" loop {}\n"
"}\n"
"```"
msgstr ""
#: src/bare-metal/microcontrollers.md:21
msgid "Next we'll look at how to access peripherals, with increasing levels of abstraction."
msgstr ""
#: src/bare-metal/microcontrollers.md:25
msgid ""
"* The `cortex_m_rt::entry` macro requires that the function have type `fn() -> !`, because "
"returning\n"
" to the reset handler doesn't make sense.\n"
"* Run the example with `cargo embed --bin minimal`"
msgstr ""
#: src/bare-metal/microcontrollers/mmio.md:1
msgid "# Raw MMIO"
msgstr ""
#: src/bare-metal/microcontrollers/mmio.md:3
msgid ""
"Most microcontrollers access peripherals via memory-mapped IO. Let's try turning on an LED on our\n"
"micro:bit:"
msgstr ""
#: src/bare-metal/microcontrollers/mmio.md:6
msgid ""
"```rust,editable,compile_fail\n"
"#![no_main]\n"
"#![no_std]\n"
"\n"
"extern crate panic_halt as _;\n"
"\n"
"mod interrupts;\n"
"\n"
"use core::mem::size_of;\n"
"use cortex_m_rt::entry;\n"
"\n"
"/// GPIO port 0 peripheral address\n"
"const GPIO_P0: usize = 0x5000_0000;\n"
"\n"
"// GPIO peripheral offsets\n"
"const PIN_CNF: usize = 0x700;\n"
"const OUTSET: usize = 0x508;\n"
"const OUTCLR: usize = 0x50c;\n"
"\n"
"// PIN_CNF fields\n"
"const DIR_OUTPUT: u32 = 0x1;\n"
"const INPUT_DISCONNECT: u32 = 0x1 << 1;\n"
"const PULL_DISABLED: u32 = 0x0 << 2;\n"
"const DRIVE_S0S1: u32 = 0x0 << 8;\n"
"const SENSE_DISABLED: u32 = 0x0 << 16;\n"
"\n"
"#[entry]\n"
"fn main() -> ! {\n"
" // Configure GPIO 0 pins 21 and 28 as push-pull outputs.\n"
" let pin_cnf_21 = (GPIO_P0 + PIN_CNF + 21 * size_of::()) as *mut u32;\n"
" let pin_cnf_28 = (GPIO_P0 + PIN_CNF + 28 * size_of::()) as *mut u32;\n"
" // Safe because the pointers are to valid peripheral control registers, and\n"
" // no aliases exist.\n"
" unsafe {\n"
" pin_cnf_21.write_volatile(\n"
" DIR_OUTPUT | INPUT_DISCONNECT | PULL_DISABLED | DRIVE_S0S1 | SENSE_DISABLED,\n"
" );\n"
" pin_cnf_28.write_volatile(\n"
" DIR_OUTPUT | INPUT_DISCONNECT | PULL_DISABLED | DRIVE_S0S1 | SENSE_DISABLED,\n"
" );\n"
" }\n"
"\n"
" // Set pin 28 low and pin 21 high to turn the LED on.\n"
" let gpio0_outset = (GPIO_P0 + OUTSET) as *mut u32;\n"
" let gpio0_outclr = (GPIO_P0 + OUTCLR) as *mut u32;\n"
" // Safe because the pointers are to valid peripheral control registers, and\n"
" // no aliases exist.\n"
" unsafe {\n"
" gpio0_outclr.write_volatile(1 << 28);\n"
" gpio0_outset.write_volatile(1 << 21);\n"
" }\n"
"\n"
" loop {}\n"
"}\n"
"```"
msgstr ""
#: src/bare-metal/microcontrollers/mmio.md:64
msgid ""
"* GPIO 0 pin 21 is connected to the first column of the LED matrix, and pin 28 to the first row."
msgstr ""
#: src/bare-metal/microcontrollers/mmio.md:66 src/bare-metal/microcontrollers/pacs.md:59
#: src/bare-metal/microcontrollers/hals.md:43 src/bare-metal/microcontrollers/board-support.md:34
msgid "Run the example with:"
msgstr ""
#: src/bare-metal/microcontrollers/mmio.md:68
#, fuzzy
msgid ""
"```sh\n"
"cargo embed --bin mmio\n"
"```"
msgstr ""
"```shell\n"
"$ cargo run\n"
"```"
#: src/bare-metal/microcontrollers/pacs.md:1
msgid "# Peripheral Access Crates"
msgstr ""
#: src/bare-metal/microcontrollers/pacs.md:3
msgid ""
"[`svd2rust`](https://crates.io/crates/svd2rust) generates mostly-safe Rust wrappers for\n"
"memory-mapped peripherals from [CMSIS-SVD](https://www.keil.com/pack/doc/CMSIS/SVD/html/index."
"html)\n"
"files."
msgstr ""
#: src/bare-metal/microcontrollers/pacs.md:7
msgid ""
"```rust,editable,compile_fail\n"
"#![no_main]\n"
"#![no_std]\n"
"\n"
"extern crate panic_halt as _;\n"
"\n"
"use cortex_m_rt::entry;\n"
"use nrf52833_pac::Peripherals;\n"
"\n"
"#[entry]\n"
"fn main() -> ! {\n"
" let p = Peripherals::take().unwrap();\n"
" let gpio0 = p.P0;\n"
"\n"
" // Configure GPIO 0 pins 21 and 28 as push-pull outputs.\n"
" gpio0.pin_cnf[21].write(|w| {\n"
" w.dir().output();\n"
" w.input().disconnect();\n"
" w.pull().disabled();\n"
" w.drive().s0s1();\n"
" w.sense().disabled();\n"
" w\n"
" });\n"
" gpio0.pin_cnf[28].write(|w| {\n"
" w.dir().output();\n"
" w.input().disconnect();\n"
" w.pull().disabled();\n"
" w.drive().s0s1();\n"
" w.sense().disabled();\n"
" w\n"
" });\n"
"\n"
" // Set pin 28 low and pin 21 high to turn the LED on.\n"
" gpio0.outclr.write(|w| w.pin28().clear());\n"
" gpio0.outset.write(|w| w.pin21().set());\n"
"\n"
" loop {}\n"
"}\n"
"```"
msgstr ""
#: src/bare-metal/microcontrollers/pacs.md:49
msgid ""
"* SVD (System View Description) files are XML files typically provided by silicon vendors which\n"
" describe the memory map of the device.\n"
" * They are organised by peripheral, register, field and value, with names, descriptions, "
"addresses\n"
" and so on.\n"
" * SVD files are often buggy and incomplete, so there are various projects which patch the\n"
" mistakes, add missing details, and publish the generated crates.\n"
"* `cortex-m-rt` provides the vector table, among other things.\n"
"* If you `cargo install cargo-binutils` then you can run\n"
" `cargo objdump --bin pac -- -d --no-show-raw-insn` to see the resulting binary."
msgstr ""
#: src/bare-metal/microcontrollers/pacs.md:61
#, fuzzy
msgid ""
"```sh\n"
"cargo embed --bin pac\n"
"```"
msgstr ""
"```shell\n"
"$ cargo run\n"
"```"
#: src/bare-metal/microcontrollers/hals.md:1
msgid "# HAL crates"
msgstr ""
#: src/bare-metal/microcontrollers/hals.md:3
msgid ""
"[HAL crates](https://github.com/rust-embedded/awesome-embedded-rust#hal-implementation-crates) "
"for\n"
"many microcontrollers provide wrappers around various peripherals. These generally implement "
"traits\n"
"from [`embedded-hal`](https://crates.io/crates/embedded-hal)."
msgstr ""
#: src/bare-metal/microcontrollers/hals.md:7
msgid ""
"```rust,editable,compile_fail\n"
"#![no_main]\n"
"#![no_std]\n"
"\n"
"extern crate panic_halt as _;\n"
"\n"
"use cortex_m_rt::entry;\n"
"use nrf52833_hal::gpio::{p0, Level};\n"
"use nrf52833_hal::pac::Peripherals;\n"
"use nrf52833_hal::prelude::*;\n"
"\n"
"#[entry]\n"
"fn main() -> ! {\n"
" let p = Peripherals::take().unwrap();\n"
"\n"
" // Create HAL wrapper for GPIO port 0.\n"
" let gpio0 = p0::Parts::new(p.P0);\n"
"\n"
" // Configure GPIO 0 pins 21 and 28 as push-pull outputs.\n"
" let mut col1 = gpio0.p0_28.into_push_pull_output(Level::High);\n"
" let mut row1 = gpio0.p0_21.into_push_pull_output(Level::Low);\n"
"\n"
" // Set pin 28 low and pin 21 high to turn the LED on.\n"
" col1.set_low().unwrap();\n"
" row1.set_high().unwrap();\n"
"\n"
" loop {}\n"
"}\n"
"```"
msgstr ""
#: src/bare-metal/microcontrollers/hals.md:39
msgid ""
" * `set_low` and `set_high` are methods on the `embedded_hal` `OutputPin` trait.\n"
" * HAL crates exist for many Cortex-M and RISC-V devices, including various STM32, GD32, nRF, "
"NXP,\n"
" MSP430, AVR and PIC microcontrollers."
msgstr ""
#: src/bare-metal/microcontrollers/hals.md:45
#, fuzzy
msgid ""
"```sh\n"
"cargo embed --bin hal\n"
"```"
msgstr ""
"```shell\n"
"$ cargo run\n"
"```"
#: src/bare-metal/microcontrollers/board-support.md:1
msgid "# Board support crates"
msgstr "# Atalhos de teclado"
#: src/bare-metal/microcontrollers/board-support.md:3
msgid ""
"Board support crates provide a further level of wrapping for a specific board for convenience."
msgstr ""
#: src/bare-metal/microcontrollers/board-support.md:5
msgid ""
"```rust,editable,compile_fail\n"
"#![no_main]\n"
"#![no_std]\n"
"\n"
"extern crate panic_halt as _;\n"
"\n"
"use cortex_m_rt::entry;\n"
"use microbit::hal::prelude::*;\n"
"use microbit::Board;\n"
"\n"
"#[entry]\n"
"fn main() -> ! {\n"
" let mut board = Board::take().unwrap();\n"
"\n"
" board.display_pins.col1.set_low().unwrap();\n"
" board.display_pins.row1.set_high().unwrap();\n"
"\n"
" loop {}\n"
"}\n"
"```"
msgstr ""
#: src/bare-metal/microcontrollers/board-support.md:28
msgid ""
" * In this case the board support crate is just providing more useful names, and a bit of\n"
" initialisation.\n"
" * The crate may also include drivers for some on-board devices outside of the microcontroller\n"
" itself.\n"
" * `microbit-v2` includes a simple driver for the LED matrix."
msgstr ""
#: src/bare-metal/microcontrollers/board-support.md:36
msgid ""
"```sh\n"
"cargo embed --bin board_support\n"
"```"
msgstr ""
#: src/bare-metal/microcontrollers/type-state.md:1
msgid "# The type state pattern"
msgstr ""
#: src/bare-metal/microcontrollers/type-state.md:3
msgid ""
"```rust,editable,compile_fail\n"
"#[entry]\n"
"fn main() -> ! {\n"
" let p = Peripherals::take().unwrap();\n"
" let gpio0 = p0::Parts::new(p.P0);\n"
"\n"
" let pin: P0_01 = gpio0.p0_01;\n"
"\n"
" // let gpio0_01_again = gpio0.p0_01; // Error, moved.\n"
" let pin_input: P0_01> = pin.into_floating_input();\n"
" if pin_input.is_high().unwrap() {\n"
" // ...\n"
" }\n"
" let mut pin_output: P0_01> = pin_input\n"
" .into_open_drain_output(OpenDrainConfig::Disconnect0Standard1, Level::Low);\n"
" pin_output.set_high().unwrap();\n"
" // pin_input.is_high(); // Error, moved.\n"
"\n"
" let _pin2: P0_02> = gpio0\n"
" .p0_02\n"
" .into_open_drain_output(OpenDrainConfig::Disconnect0Standard1, Level::Low);\n"
" let _pin3: P0_03> = gpio0.p0_03.into_push_pull_output(Level::Low);\n"
"\n"
" loop {}\n"
"}\n"
"```"
msgstr ""
#: src/bare-metal/microcontrollers/type-state.md:32
msgid ""
" * Pins don't implement `Copy` or `Clone`, so only one instance of each can exist. Once a pin is\n"
" moved out of the port struct nobody else can take it.\n"
" * Changing the configuration of a pin consumes the old pin instance, so you can’t keep use the "
"old\n"
" instance afterwards.\n"
" * The type of a value indicates the state that it is in: e.g. in this case, the configuration "
"state\n"
" of a GPIO pin. This encodes the state machine into the type system, and ensures that you don't\n"
" try to use a pin in a certain way without properly configuring it first. Illegal state\n"
" transitions are caught at compile time.\n"
" * You can call `is_high` on an input pin and `set_high` on an output pin, but not vice-versa.\n"
" * Many HAL crates follow this pattern."
msgstr ""
#: src/bare-metal/microcontrollers/embedded-hal.md:1
msgid "# `embedded-hal`"
msgstr ""
#: src/bare-metal/microcontrollers/embedded-hal.md:3
msgid ""
"The [`embedded-hal`](https://crates.io/crates/embedded-hal) crate provides a number of traits\n"
"covering common microcontroller peripherals."
msgstr ""
#: src/bare-metal/microcontrollers/embedded-hal.md:6
msgid ""
" * GPIO\n"
" * ADC\n"
" * I2C, SPI, UART, CAN\n"
" * RNG\n"
" * Timers\n"
" * Watchdogs"
msgstr ""
#: src/bare-metal/microcontrollers/embedded-hal.md:13
msgid ""
"Other crates then implement\n"
"[drivers](https://github.com/rust-embedded/awesome-embedded-rust#driver-crates) in terms of these\n"
"traits, e.g. an accelerometer driver might need an I2C or SPI bus implementation."
msgstr ""
#: src/bare-metal/microcontrollers/embedded-hal.md:19
msgid ""
" * There are implementations for many microcontrollers, as well as other platforms such as Linux "
"on\n"
"Raspberry Pi.\n"
" * There is work in progress on an `async` version of `embedded-hal`, but it isn't stable yet."
msgstr ""
#: src/bare-metal/microcontrollers/probe-rs.md:1
msgid "# `probe-rs`, `cargo-embed`"
msgstr ""
#: src/bare-metal/microcontrollers/probe-rs.md:3
msgid ""
"[probe-rs](https://probe.rs/) is a handy toolset for embedded debugging, like OpenOCD but better\n"
"integrated."
msgstr ""
#: src/bare-metal/microcontrollers/probe-rs.md:6
msgid ""
"* SWD and JTAG via CMSIS-DAP, ST-Link and J-Link probes\n"
"* GDB stub and Microsoft DAP server\n"
"* Cargo integration"
msgstr ""
#: src/bare-metal/microcontrollers/probe-rs.md:10
msgid ""
"`cargo-embed` is a cargo subcommand to build and flash binaries, log\n"
"RTT output and connect GDB. It's configured by an\n"
"`Embed.toml` file in your project directory."
msgstr ""
#: src/bare-metal/microcontrollers/probe-rs.md:16
msgid ""
"* [CMSIS-DAP](https://arm-software.github.io/CMSIS_5/DAP/html/index.html) is an Arm standard\n"
" protocol over USB for an in-circuit debugger to access the CoreSight Debug Access Port of "
"various\n"
" Arm Cortex processors. It's what the on-board debugger on the BBC micro:bit uses.\n"
"* ST-Link is a range of in-circuit debuggers from ST Microelectronics, J-Link is a range from\n"
" SEGGER.\n"
"* The Debug Access Port is usually either a 5-pin JTAG interface or 2-pin Serial Wire Debug.\n"
"* probe-rs is a library which you can integrate into your own tools if you want to.\n"
"* The [Microsoft Debug Adapter Protocol](https://microsoft.github.io/debug-adapter-protocol/) "
"lets\n"
" VSCode and other IDEs debug code running on any supported microcontroller.\n"
"* cargo-embed is a binary built using the probe-rs library.\n"
"* RTT (Real Time Transfers) is a mechanism to transfer data between the debug host and the target\n"
" through a number of ringbuffers."
msgstr ""
#: src/bare-metal/microcontrollers/debugging.md:1
#, fuzzy
msgid "# Debugging"
msgstr "# Gerando registros (Log)"
#: src/bare-metal/microcontrollers/debugging.md:3
msgid "Embed.toml:"
msgstr ""
#: src/bare-metal/microcontrollers/debugging.md:5
msgid ""
"```toml\n"
"[default.general]\n"
"chip = \"nrf52833_xxAA\"\n"
"\n"
"[debug.gdb]\n"
"enabled = true\n"
"```"
msgstr ""
#: src/bare-metal/microcontrollers/debugging.md:13
msgid "In one terminal under `src/bare-metal/microcontrollers/examples/`:"
msgstr ""
#: src/bare-metal/microcontrollers/debugging.md:15
msgid ""
"```sh\n"
"cargo embed --bin board_support debug\n"
"```"
msgstr ""
#: src/bare-metal/microcontrollers/debugging.md:19
#, fuzzy
msgid "In another terminal in the same directory:"
msgstr "Em outro terminal, verifique se o serviço é executado:"
#: src/bare-metal/microcontrollers/debugging.md:21
msgid ""
"```sh\n"
"gdb-multiarch target/thumbv7em-none-eabihf/debug/board_support --eval-command=\"target "
"remote :1337\"\n"
"```"
msgstr ""
#: src/bare-metal/microcontrollers/debugging.md:27
msgid "In GDB, try running:"
msgstr ""
#: src/bare-metal/microcontrollers/debugging.md:29
msgid ""
"```gdb\n"
"b src/bin/board_support.rs:29\n"
"b src/bin/board_support.rs:30\n"
"b src/bin/board_support.rs:32\n"
"c\n"
"c\n"
"c\n"
"```"
msgstr ""
#: src/bare-metal/microcontrollers/other-projects.md:1 src/bare-metal/aps/other-projects.md:1
msgid "# Other projects"
msgstr ""
#: src/bare-metal/microcontrollers/other-projects.md:3
msgid ""
" * [RTIC](https://rtic.rs/)\n"
" * \"Real-Time Interrupt-driven Concurrency\"\n"
" * Shared resource management, message passing, task scheduling, timer queue\n"
" * [Embassy](https://embassy.dev/)\n"
" * `async` executors with priorities, timers, networking, USB\n"
" * [TockOS](https://www.tockos.org/documentation/getting-started)\n"
" * Security-focused RTOS with preemptive scheduling and Memory Protection Unit support\n"
" * [Hubris](https://hubris.oxide.computer/)\n"
" * Microkernel RTOS from Oxide Computer Company with memory protection, unprivileged drivers, "
"IPC\n"
" * [Bindings for FreeRTOS](https://github.com/lobaro/FreeRTOS-rust)\n"
" * Some platforms have `std` implementations, e.g.\n"
" [esp-idf](https://esp-rs.github.io/book/overview/using-the-standard-library.html)."
msgstr ""
#: src/bare-metal/microcontrollers/other-projects.md:18
msgid ""
" * RTIC can be considered either an RTOS or a concurrency framework.\n"
" * It doesn't include any HALs.\n"
" * It uses the Cortex-M NVIC (Nested Virtual Interrupt Controller) for scheduling rather than a\n"
" proper kernel.\n"
" * Cortex-M only.\n"
" * Google uses TockOS on the Haven microcontroller for Titan security keys.\n"
" * FreeRTOS is mostly written in C, but there are Rust bindings for writing applications."
msgstr ""
#: src/exercises/bare-metal/morning.md:3
msgid "We will read the direction from an I2C compass, and log the readings to a serial port."
msgstr ""
#: src/exercises/bare-metal/compass.md:1
#, fuzzy
msgid "# Compass"
msgstr "# Comparação"
#: src/exercises/bare-metal/compass.md:3
msgid ""
"We will read the direction from an I2C compass, and log the readings to a serial port. If you "
"have\n"
"time, try displaying it on the LEDs somehow too, or use the buttons somehow."
msgstr ""
#: src/exercises/bare-metal/compass.md:6
msgid "Hints:"
msgstr ""
#: src/exercises/bare-metal/compass.md:8
msgid ""
"- Check the documentation for the [`lsm303agr`](https://docs.rs/lsm303agr/latest/lsm303agr/) and\n"
" [`microbit-v2`](https://docs.rs/microbit-v2/latest/microbit/) crates, as well as the\n"
" [micro:bit hardware](https://tech.microbit.org/hardware/).\n"
"- The LSM303AGR Inertial Measurement Unit is connected to the internal I2C bus.\n"
"- TWI is another name for I2C, so the I2C master peripheral is called TWIM.\n"
"- The LSM303AGR driver needs something implementing the `embedded_hal::blocking::i2c::WriteRead`\n"
" trait. The\n"
" [`microbit::hal::Twim`](https://docs.rs/microbit-v2/latest/microbit/hal/struct.Twim.html) "
"struct\n"
" implements this.\n"
"- You have a [`microbit::Board`](https://docs.rs/microbit-v2/latest/microbit/struct.Board.html)\n"
" struct with fields for the various pins and peripherals.\n"
"- You can also look at the\n"
" [nRF52833 datasheet](https://infocenter.nordicsemi.com/pdf/nRF52833_PS_v1.5.pdf) if you want, "
"but\n"
" it shouldn't be necessary for this exercise."
msgstr ""
#: src/exercises/bare-metal/compass.md:23
msgid ""
"Download the [exercise template](../../comprehensive-rust-exercises.zip) and look in the "
"`compass`\n"
"directory for the following files."
msgstr ""
#: src/exercises/bare-metal/compass.md:26 src/exercises/bare-metal/rtc.md:19
#, fuzzy
msgid "`src/main.rs`:"
msgstr "_hello_rust/src/main.rs_:"
#: src/exercises/bare-metal/compass.md:28 src/exercises/bare-metal/rtc.md:21
#: src/exercises/concurrency/dining-philosophers.md:17 src/exercises/concurrency/link-checker.md:55
#: src/exercises/concurrency/dining-philosophers-async.md:11
msgid ""
msgstr ""
#: src/exercises/bare-metal/compass.md:30
msgid ""
"```rust,compile_fail\n"
"#![no_main]\n"
"#![no_std]\n"
"\n"
"extern crate panic_halt as _;\n"
"\n"
"use core::fmt::Write;\n"
"use cortex_m_rt::entry;\n"
"use microbit::{hal::uarte::{Baudrate, Parity, Uarte}, Board};\n"
"\n"
"#[entry]\n"
"fn main() -> ! {\n"
" let board = Board::take().unwrap();\n"
"\n"
" // Configure serial port.\n"
" let mut serial = Uarte::new(\n"
" board.UARTE0,\n"
" board.uart.into(),\n"
" Parity::EXCLUDED,\n"
" Baudrate::BAUD115200,\n"
" );\n"
"\n"
" // Set up the I2C controller and Inertial Measurement Unit.\n"
" // TODO\n"
"\n"
" writeln!(serial, \"Ready.\").unwrap();\n"
"\n"
" loop {\n"
" // Read compass data and log it to the serial port.\n"
" // TODO\n"
" }\n"
"}\n"
"```"
msgstr ""
#: src/exercises/bare-metal/compass.md:64 src/exercises/bare-metal/rtc.md:385
msgid "`Cargo.toml` (you shouldn't need to change this):"
msgstr ""
#: src/exercises/bare-metal/compass.md:66 src/exercises/bare-metal/rtc.md:387
#: src/exercises/concurrency/dining-philosophers.md:63 src/exercises/concurrency/link-checker.md:35
#: src/exercises/concurrency/dining-philosophers-async.md:60 src/exercises/concurrency/chat-app.md:17
msgid ""
msgstr ""
#: src/exercises/bare-metal/compass.md:68
msgid ""
"```toml\n"
"[workspace]\n"
"\n"
"[package]\n"
"name = \"compass\"\n"
"version = \"0.1.0\"\n"
"edition = \"2021\"\n"
"publish = false\n"
"\n"
"[dependencies]\n"
"cortex-m-rt = \"0.7.3\"\n"
"embedded-hal = \"0.2.6\"\n"
"lsm303agr = \"0.2.2\"\n"
"microbit-v2 = \"0.13.0\"\n"
"panic-halt = \"0.2.0\"\n"
"```"
msgstr ""
#: src/exercises/bare-metal/compass.md:85
msgid "`Embed.toml` (you shouldn't need to change this):"
msgstr ""
#: src/exercises/bare-metal/compass.md:87
msgid ""
msgstr ""
#: src/exercises/bare-metal/compass.md:89
msgid ""
"```toml\n"
"[default.general]\n"
"chip = \"nrf52833_xxAA\"\n"
"\n"
"[debug.gdb]\n"
"enabled = true\n"
"\n"
"[debug.reset]\n"
"halt_afterwards = true\n"
"```"
msgstr ""
#: src/exercises/bare-metal/compass.md:100 src/exercises/bare-metal/rtc.md:985
msgid "`.cargo/config.toml` (you shouldn't need to change this):"
msgstr ""
#: src/exercises/bare-metal/compass.md:102 src/exercises/bare-metal/rtc.md:987
msgid ""
msgstr ""
#: src/exercises/bare-metal/compass.md:104
msgid ""
"```toml\n"
"[build]\n"
"target = \"thumbv7em-none-eabihf\" # Cortex-M4F\n"
"\n"
"[target.'cfg(all(target_arch = \"arm\", target_os = \"none\"))']\n"
"rustflags = [\"-C\", \"link-arg=-Tlink.x\"]\n"
"```"
msgstr ""
#: src/exercises/bare-metal/compass.md:112
msgid "See the serial output on Linux with:"
msgstr ""
#: src/exercises/bare-metal/compass.md:114
msgid ""
"```sh\n"
"picocom --baud 115200 --imap lfcrlf /dev/ttyACM0\n"
"```"
msgstr ""
#: src/exercises/bare-metal/compass.md:118
msgid "Or on Mac OS something like (the device name may be slightly different):"
msgstr ""
#: src/exercises/bare-metal/compass.md:120
msgid ""
"```sh\n"
"picocom --baud 115200 --imap lfcrlf /dev/tty.usbmodem14502\n"
"```"
msgstr ""
#: src/exercises/bare-metal/compass.md:124
msgid "Use Ctrl+A Ctrl+Q to quit picocom."
msgstr ""
#: src/bare-metal/aps.md:1
msgid "# Application processors"
msgstr ""
#: src/bare-metal/aps.md:3
msgid ""
"So far we've talked about microcontrollers, such as the Arm Cortex-M series. Now let's try "
"writing\n"
"something for Cortex-A. For simplicity we'll just work with QEMU's aarch64\n"
"['virt'](https://qemu-project.gitlab.io/qemu/system/arm/virt.html) board."
msgstr ""
#: src/bare-metal/aps.md:9
msgid ""
"* Broadly speaking, microcontrollers don't have an MMU or multiple levels of privilege (exception\n"
" levels on Arm CPUs, rings on x86), while application processors do.\n"
"* QEMU supports emulating various different machines or board models for each architecture. The\n"
" 'virt' board doesn't correspond to any particular real hardware, but is designed purely for\n"
" virtual machines."
msgstr ""
#: src/bare-metal/aps/entry-point.md:1
msgid "# Getting Ready to Rust"
msgstr ""
#: src/bare-metal/aps/entry-point.md:3
msgid "Before we can start running Rust code, we need to do some initialisation."
msgstr ""
#: src/bare-metal/aps/entry-point.md:5
msgid ""
"```armasm\n"
".section .init.entry, \"ax\"\n"
".global entry\n"
"entry:\n"
" /*\n"
" * Load and apply the memory management configuration, ready to enable MMU and\n"
" * caches.\n"
" */\n"
" adrp x30, idmap\n"
" msr ttbr0_el1, x30\n"
"\n"
" mov_i x30, .Lmairval\n"
" msr mair_el1, x30\n"
"\n"
" mov_i x30, .Ltcrval\n"
" /* Copy the supported PA range into TCR_EL1.IPS. */\n"
" mrs x29, id_aa64mmfr0_el1\n"
" bfi x30, x29, #32, #4\n"
"\n"
" msr tcr_el1, x30\n"
"\n"
" mov_i x30, .Lsctlrval\n"
"\n"
" /*\n"
" * Ensure everything before this point has completed, then invalidate any\n"
" * potentially stale local TLB entries before they start being used.\n"
" */\n"
" isb\n"
" tlbi vmalle1\n"
" ic iallu\n"
" dsb nsh\n"
" isb\n"
"\n"
" /*\n"
" * Configure sctlr_el1 to enable MMU and cache and don't proceed until this\n"
" * has completed.\n"
" */\n"
" msr sctlr_el1, x30\n"
" isb\n"
"\n"
" /* Disable trapping floating point access in EL1. */\n"
" mrs x30, cpacr_el1\n"
" orr x30, x30, #(0x3 << 20)\n"
" msr cpacr_el1, x30\n"
" isb\n"
"\n"
" /* Zero out the bss section. */\n"
" adr_l x29, bss_begin\n"
" adr_l x30, bss_end\n"
"0: cmp x29, x30\n"
" b.hs 1f\n"
" stp xzr, xzr, [x29], #16\n"
" b 0b\n"
"\n"
"1: /* Prepare the stack. */\n"
" adr_l x30, boot_stack_end\n"
" mov sp, x30\n"
"\n"
" /* Set up exception vector. */\n"
" adr x30, vector_table_el1\n"
" msr vbar_el1, x30\n"
"\n"
" /* Call into Rust code. */\n"
" bl main\n"
"\n"
" /* Loop forever waiting for interrupts. */\n"
"2: wfi\n"
" b 2b\n"
"```"
msgstr ""
#: src/bare-metal/aps/entry-point.md:77
msgid ""
"* This is the same as it would be for C: initialising the processor state, zeroing the BSS, and\n"
" setting up the stack pointer.\n"
" * The BSS (block starting symbol, for historical reasons) is the part of the object file which\n"
" containing statically allocated variables which are initialised to zero. They are omitted "
"from\n"
" the image, to avoid wasting space on zeroes. The compiler assumes that the loader will take "
"care\n"
" of zeroing them.\n"
"* The BSS may already be zeroed, depending on how memory is initialised and the image is loaded, "
"but\n"
" we zero it to be sure.\n"
"* We need to enable the MMU and cache before reading or writing any memory. If we don't:\n"
" * Unaligned accesses will fault. We build the Rust code for the `aarch64-unknown-none` target\n"
" which sets `+strict-align` to prevent the compiler generating unaligned accesses, so it "
"should\n"
" be fine in this case, but this is not necessarily the case in general.\n"
" * If it were running in a VM, this can lead to cache coherency issues. The problem is that the "
"VM\n"
" is accessing memory directly with the cache disabled, while the host has cachable aliases to "
"the\n"
" same memory. Even if the host doesn't explicitly access the memory, speculative accesses can\n"
" lead to cache fills, and then changes from one or the other will get lost when the cache is\n"
" cleaned or the VM enables the cache. (Cache is keyed by physical address, not VA or IPA.)\n"
"* For simplicity, we just use a hardcoded pagetable (see `idmap.S`) which identity maps the first "
"1\n"
" GiB of address space for devices, the next 1 GiB for DRAM, and another 1 GiB higher up for more\n"
" devices. This matches the memory layout that QEMU uses.\n"
"* We also set up the exception vector (`vbar_el1`), which we'll see more about later.\n"
"* All examples this afternoon assume we will be running at exception level 1 (EL1). If you need "
"to\n"
" run at a different exception level you'll need to modify `entry.S` accordingly."
msgstr ""
#: src/bare-metal/aps/inline-assembly.md:1
msgid "# Inline assembly"
msgstr ""
#: src/bare-metal/aps/inline-assembly.md:3
msgid ""
"Sometimes we need to use assembly to do things that aren't possible with Rust code. For example,\n"
"to make an HVC to tell the firmware to power off the system:"
msgstr ""
#: src/bare-metal/aps/inline-assembly.md:6
msgid ""
"```rust,editable,compile_fail\n"
"#![no_main]\n"
"#![no_std]\n"
"\n"
"use core::arch::asm;\n"
"use core::panic::PanicInfo;\n"
"\n"
"mod exceptions;\n"
"\n"
"const PSCI_SYSTEM_OFF: u32 = 0x84000008;\n"
"\n"
"#[no_mangle]\n"
"extern \"C\" fn main(_x0: u64, _x1: u64, _x2: u64, _x3: u64) {\n"
" // Safe because this only uses the declared registers and doesn't do\n"
" // anything with memory.\n"
" unsafe {\n"
" asm!(\"hvc #0\",\n"
" inout(\"w0\") PSCI_SYSTEM_OFF => _,\n"
" inout(\"w1\") 0 => _,\n"
" inout(\"w2\") 0 => _,\n"
" inout(\"w3\") 0 => _,\n"
" inout(\"w4\") 0 => _,\n"
" inout(\"w5\") 0 => _,\n"
" inout(\"w6\") 0 => _,\n"
" inout(\"w7\") 0 => _,\n"
" options(nomem, nostack)\n"
" );\n"
" }\n"
"\n"
" loop {}\n"
"}\n"
"```"
msgstr ""
#: src/bare-metal/aps/inline-assembly.md:39
msgid ""
"(If you actually want to do this, use the [`smccc`][1] crate which has wrappers for all these "
"functions.)"
msgstr ""
#: src/bare-metal/aps/inline-assembly.md:43
msgid ""
"* PSCI is the Arm Power State Coordination Interface, a standard set of functions to manage "
"system\n"
" and CPU power states, among other things. It is implemented by EL3 firmware and hypervisors on\n"
" many systems.\n"
"* The `0 => _` syntax means initialise the register to 0 before running the inline assembly code,\n"
" and ignore its contents afterwards. We need to use `inout` rather than `in` because the call "
"could\n"
" potentially clobber the contents of the registers.\n"
"* This `main` function needs to be `#[no_mangle]` and `extern \"C\"` because it is called from "
"our\n"
" entry point in `entry.S`.\n"
"* `_x0`–`_x3` are the values of registers `x0`–`x3`, which are conventionally used by the "
"bootloader\n"
" to pass things like a pointer to the device tree. According to the standard aarch64 calling\n"
" convention (which is what `extern \"C\"` specifies to use), registers `x0`–`x7` are used for "
"the\n"
" first 8 arguments passed to a function, so `entry.S` doesn't need to do anything special except\n"
" make sure it doesn't change these registers.\n"
"* Run the example in QEMU with `make qemu_psci` under `src/bare-metal/aps/examples`."
msgstr ""
#: src/bare-metal/aps/mmio.md:1
msgid "# Volatile memory access for MMIO"
msgstr ""
#: src/bare-metal/aps/mmio.md:3
msgid ""
" * Use `pointer::read_volatile` and `pointer::write_volatile`.\n"
" * Never hold a reference.\n"
" * `addr_of!` lets you get fields of structs without creating an intermediate reference."
msgstr ""
#: src/bare-metal/aps/mmio.md:9
msgid ""
" * Volatile access: read or write operations may have side-effects, so prevent the compiler or\n"
" hardware from reordering, duplicating or eliding them.\n"
" * Usually if you write and then read, e.g. via a mutable reference, the compiler may assume "
"that\n"
" the value read is the same as the value just written, and not bother actually reading "
"memory.\n"
" * Some existing crates for volatile access to hardware do hold references, but this is unsound.\n"
" Whenever a reference exist, the compiler may choose to dereference it.\n"
" * Use the `addr_of!` macro to get struct field pointers from a pointer to the struct."
msgstr ""
#: src/bare-metal/aps/uart.md:1
msgid "# Let's write a UART driver"
msgstr ""
#: src/bare-metal/aps/uart.md:3
msgid "The QEMU 'virt' machine has a [PL011][1] UART, so let's write a driver for that."
msgstr ""
#: src/bare-metal/aps/uart.md:5
msgid ""
"```rust,editable\n"
"const FLAG_REGISTER_OFFSET: usize = 0x18;\n"
"const FR_BUSY: u8 = 1 << 3;\n"
"const FR_TXFF: u8 = 1 << 5;\n"
"\n"
"/// Minimal driver for a PL011 UART.\n"
"#[derive(Debug)]\n"
"pub struct Uart {\n"
" base_address: *mut u8,\n"
"}\n"
"\n"
"impl Uart {\n"
" /// Constructs a new instance of the UART driver for a PL011 device at the\n"
" /// given base address.\n"
" ///\n"
" /// # Safety\n"
" ///\n"
" /// The given base address must point to the 8 MMIO control registers of a\n"
" /// PL011 device, which must be mapped into the address space of the process\n"
" /// as device memory and not have any other aliases.\n"
" pub unsafe fn new(base_address: *mut u8) -> Self {\n"
" Self { base_address }\n"
" }\n"
"\n"
" /// Writes a single byte to the UART.\n"
" pub fn write_byte(&self, byte: u8) {\n"
" // Wait until there is room in the TX buffer.\n"
" while self.read_flag_register() & FR_TXFF != 0 {}\n"
"\n"
" // Safe because we know that the base address points to the control\n"
" // registers of a PL011 device which is appropriately mapped.\n"
" unsafe {\n"
" // Write to the TX buffer.\n"
" self.base_address.write_volatile(byte);\n"
" }\n"
"\n"
" // Wait until the UART is no longer busy.\n"
" while self.read_flag_register() & FR_BUSY != 0 {}\n"
" }\n"
"\n"
" fn read_flag_register(&self) -> u8 {\n"
" // Safe because we know that the base address points to the control\n"
" // registers of a PL011 device which is appropriately mapped.\n"
" unsafe { self.base_address.add(FLAG_REGISTER_OFFSET).read_volatile() }\n"
" }\n"
"}\n"
"```"
msgstr ""
#: src/bare-metal/aps/uart.md:55
msgid ""
"* Note that `Uart::new` is unsafe while the other methods are safe. This is because as long as "
"the\n"
" caller of `Uart::new` guarantees that its safety requirements are met (i.e. that there is only\n"
" ever one instance of the driver for a given UART, and nothing else aliasing its address space),\n"
" then it is always safe to call `write_byte` later because we can assume the necessary\n"
" preconditions.\n"
"* We could have done it the other way around (making `new` safe but `write_byte` unsafe), but "
"that\n"
" would be much less convenient to use as every place that calls `write_byte` would need to "
"reason\n"
" about the safety\n"
"* This is a common pattern for writing safe wrappers of unsafe code: moving the burden of proof "
"for\n"
" soundness from a large number of places to a smaller number of places."
msgstr ""
#: src/bare-metal/aps/uart.md:66
#, fuzzy
msgid ""
msgstr "
"
#: src/bare-metal/aps/uart/traits.md:1
#, fuzzy
msgid "# More traits"
msgstr "# Traits (Características)"
#: src/bare-metal/aps/uart/traits.md:3
msgid "We derived the `Debug` trait. It would be useful to implement a few more traits too."
msgstr ""
#: src/bare-metal/aps/uart/traits.md:5
msgid ""
"```rust,editable,compile_fail\n"
"use core::fmt::{self, Write};\n"
"\n"
"impl Write for Uart {\n"
" fn write_str(&mut self, s: &str) -> fmt::Result {\n"
" for c in s.as_bytes() {\n"
" self.write_byte(*c);\n"
" }\n"
" Ok(())\n"
" }\n"
"}\n"
"\n"
"// Safe because it just contains a pointer to device memory, which can be\n"
"// accessed from any context.\n"
"unsafe impl Send for Uart {}\n"
"```"
msgstr ""
#: src/bare-metal/aps/uart/traits.md:24
msgid ""
"* Implementing `Write` lets us use the `write!` and `writeln!` macros with our `Uart` type.\n"
"* Run the example in QEMU with `make qemu_minimal` under `src/bare-metal/aps/examples`."
msgstr ""
#: src/bare-metal/aps/better-uart.md:1
msgid "# A better UART driver"
msgstr ""
#: src/bare-metal/aps/better-uart.md:3
msgid ""
"The PL011 actually has [a bunch more registers][1], and adding offsets to construct pointers to "
"access\n"
"them is error-prone and hard to read. Plus, some of them are bit fields which would be nice to\n"
"access in a structured way."
msgstr ""
#: src/bare-metal/aps/better-uart.md:7
msgid ""
"| Offset | Register name | Width |\n"
"| ------ | ------------- | ----- |\n"
"| 0x00 | DR | 12 |\n"
"| 0x04 | RSR | 4 |\n"
"| 0x18 | FR | 9 |\n"
"| 0x20 | ILPR | 8 |\n"
"| 0x24 | IBRD | 16 |\n"
"| 0x28 | FBRD | 6 |\n"
"| 0x2c | LCR_H | 8 |\n"
"| 0x30 | CR | 16 |\n"
"| 0x34 | IFLS | 6 |\n"
"| 0x38 | IMSC | 11 |\n"
"| 0x3c | RIS | 11 |\n"
"| 0x40 | MIS | 11 |\n"
"| 0x44 | ICR | 11 |\n"
"| 0x48 | DMACR | 3 |"
msgstr ""
#: src/bare-metal/aps/better-uart.md:26
msgid "- There are also some ID registers which have been omitted for brevity."
msgstr ""
#: src/bare-metal/aps/better-uart/bitflags.md:1
msgid "# Bitflags"
msgstr ""
#: src/bare-metal/aps/better-uart/bitflags.md:3
msgid ""
"The [`bitflags`](https://crates.io/crates/bitflags) crate is useful for working with bitflags."
msgstr ""
#: src/bare-metal/aps/better-uart/bitflags.md:5
msgid ""
"```rust,editable,compile_fail\n"
"use bitflags::bitflags;\n"
"\n"
"bitflags! {\n"
" /// Flags from the UART flag register.\n"
" #[repr(transparent)]\n"
" #[derive(Copy, Clone, Debug, Eq, PartialEq)]\n"
" struct Flags: u16 {\n"
" /// Clear to send.\n"
" const CTS = 1 << 0;\n"
" /// Data set ready.\n"
" const DSR = 1 << 1;\n"
" /// Data carrier detect.\n"
" const DCD = 1 << 2;\n"
" /// UART busy transmitting data.\n"
" const BUSY = 1 << 3;\n"
" /// Receive FIFO is empty.\n"
" const RXFE = 1 << 4;\n"
" /// Transmit FIFO is full.\n"
" const TXFF = 1 << 5;\n"
" /// Receive FIFO is full.\n"
" const RXFF = 1 << 6;\n"
" /// Transmit FIFO is empty.\n"
" const TXFE = 1 << 7;\n"
" /// Ring indicator.\n"
" const RI = 1 << 8;\n"
" }\n"
"}\n"
"```"
msgstr ""
#: src/bare-metal/aps/better-uart/bitflags.md:37
msgid ""
"* The `bitflags!` macro creates a newtype something like `Flags(u16)`, along with a bunch of "
"method\n"
" implementations to get and set flags."
msgstr ""
#: src/bare-metal/aps/better-uart/registers.md:1
msgid "# Multiple registers"
msgstr ""
#: src/bare-metal/aps/better-uart/registers.md:3
msgid "We can use a struct to represent the memory layout of the UART's registers."
msgstr ""
#: src/bare-metal/aps/better-uart/registers.md:5
msgid ""
"```rust,editable,compile_fail\n"
"#[repr(C, align(4))]\n"
"struct Registers {\n"
" dr: u16,\n"
" _reserved0: [u8; 2],\n"
" rsr: ReceiveStatus,\n"
" _reserved1: [u8; 19],\n"
" fr: Flags,\n"
" _reserved2: [u8; 6],\n"
" ilpr: u8,\n"
" _reserved3: [u8; 3],\n"
" ibrd: u16,\n"
" _reserved4: [u8; 2],\n"
" fbrd: u8,\n"
" _reserved5: [u8; 3],\n"
" lcr_h: u8,\n"
" _reserved6: [u8; 3],\n"
" cr: u16,\n"
" _reserved7: [u8; 3],\n"
" ifls: u8,\n"
" _reserved8: [u8; 3],\n"
" imsc: u16,\n"
" _reserved9: [u8; 2],\n"
" ris: u16,\n"
" _reserved10: [u8; 2],\n"
" mis: u16,\n"
" _reserved11: [u8; 2],\n"
" icr: u16,\n"
" _reserved12: [u8; 2],\n"
" dmacr: u8,\n"
" _reserved13: [u8; 3],\n"
"}\n"
"```"
msgstr ""
#: src/bare-metal/aps/better-uart/registers.md:41
msgid ""
"* [`#[repr(C)]`](https://doc.rust-lang.org/reference/type-layout.html#the-c-representation) tells\n"
" the compiler to lay the struct fields out in order, following the same rules as C. This is\n"
" necessary for our struct to have a predictable layout, as default Rust representation allows "
"the\n"
" compiler to (among other things) reorder fields however it sees fit."
msgstr ""
#: src/bare-metal/aps/better-uart/driver.md:1
msgid "# Driver"
msgstr ""
#: src/bare-metal/aps/better-uart/driver.md:3
msgid "Now let's use the new `Registers` struct in our driver."
msgstr ""
#: src/bare-metal/aps/better-uart/driver.md:5
msgid ""
"```rust,editable,compile_fail\n"
"/// Driver for a PL011 UART.\n"
"#[derive(Debug)]\n"
"pub struct Uart {\n"
" registers: *mut Registers,\n"
"}\n"
"\n"
"impl Uart {\n"
" /// Constructs a new instance of the UART driver for a PL011 device at the\n"
" /// given base address.\n"
" ///\n"
" /// # Safety\n"
" ///\n"
" /// The given base address must point to the 8 MMIO control registers of a\n"
" /// PL011 device, which must be mapped into the address space of the process\n"
" /// as device memory and not have any other aliases.\n"
" pub unsafe fn new(base_address: *mut u32) -> Self {\n"
" Self {\n"
" registers: base_address as *mut Registers,\n"
" }\n"
" }\n"
"\n"
" /// Writes a single byte to the UART.\n"
" pub fn write_byte(&self, byte: u8) {\n"
" // Wait until there is room in the TX buffer.\n"
" while self.read_flag_register().contains(Flags::TXFF) {}\n"
"\n"
" // Safe because we know that self.registers points to the control\n"
" // registers of a PL011 device which is appropriately mapped.\n"
" unsafe {\n"
" // Write to the TX buffer.\n"
" addr_of_mut!((*self.registers).dr).write_volatile(byte.into());\n"
" }\n"
"\n"
" // Wait until the UART is no longer busy.\n"
" while self.read_flag_register().contains(Flags::BUSY) {}\n"
" }\n"
"\n"
" /// Reads and returns a pending byte, or `None` if nothing has been received.\n"
" pub fn read_byte(&self) -> Option\n"
" \n"
"* A razão para isso é que, quando a função `thread::scope` for concluída, todas as _threads_ serão "
"unidas, para que possam retornar dados emprestados.\n"
"* Aplicam-se as regras normais de empréstimo do Rust: o empréstimo pode ser mutável, para uma "
"`thread` ou imutável para\n"
"qualquer número de _threads_.\n"
" \n"
"
"
#: src/concurrency/channels.md:1
msgid "# Channels"
msgstr "# Channels (Canais)"
#: src/concurrency/channels.md:3
msgid ""
"Rust channels have two parts: a `Sender