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Code Issues Releases Activity

Add SystemVerilog (SV) type

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This commit is contained in:
Kaushal Modi 2016-09-26 15:24:35 -04:00
parent a41235a3b5
commit ec26995655
1 changed files with 1 additions and 0 deletions
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src/types.rs
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@ -70,6 +70,7 @@ const TYPE_EXTENSIONS: &'static [(&'static str, &'static [&'static str])] = &[
("scala", &["*.scala"]),
("sh", &["*.bash", "*.csh", "*.ksh", "*.sh", "*.tcsh"]),
("sql", &["*.sql"]),
("sv", &["*.v", "*.vg", "*.sv", "*.svh", "*.h"]),
("swift", &["*.swift"]),
("tex", &["*.tex", "*.cls", "*.sty"]),
("ts", &["*.ts", "*.tsx"]),