mirror of
https://github.com/FFmpeg/FFmpeg.git
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229 lines
7.2 KiB
ArmAsm
229 lines
7.2 KiB
ArmAsm
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/*
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* ARM NEON optimised IDCT functions for HEVC decoding
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* Copyright (c) 2017 Alexandra Hájková
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*
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* This file is part of Libav.
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*
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* Libav is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* Libav is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with Libav; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include "libavutil/arm/asm.S"
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const trans, align=4
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.short 64, 83, 64, 36
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.short 89, 75, 50, 18
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.short 90, 87, 80, 70
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.short 57, 43, 25, 9
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endconst
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.macro sum_sub out, in, c, op
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.ifc \op, +
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vmlal.s16 \out, \in, \c
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.else
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vmlsl.s16 \out, \in, \c
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.endif
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.endm
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.macro tr_4x4 in0, in1, in2, in3, out0, out1, out2, out3, shift, tmp0, tmp1, tmp2, tmp3, tmp4
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vshll.s16 \tmp0, \in0, #6
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vmull.s16 \tmp2, \in1, d4[1]
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vmov \tmp1, \tmp0
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vmull.s16 \tmp3, \in1, d4[3]
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vmlal.s16 \tmp0, \in2, d4[0] @e0
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vmlsl.s16 \tmp1, \in2, d4[0] @e1
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vmlal.s16 \tmp2, \in3, d4[3] @o0
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vmlsl.s16 \tmp3, \in3, d4[1] @o1
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vadd.s32 \tmp4, \tmp0, \tmp2
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vsub.s32 \tmp0, \tmp0, \tmp2
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vadd.s32 \tmp2, \tmp1, \tmp3
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vsub.s32 \tmp1, \tmp1, \tmp3
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vqrshrn.s32 \out0, \tmp4, #\shift
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vqrshrn.s32 \out3, \tmp0, #\shift
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vqrshrn.s32 \out1, \tmp2, #\shift
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vqrshrn.s32 \out2, \tmp1, #\shift
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.endm
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.macro tr_4x4_8 in0, in1, in2, in3, out0, out1, out2, out3, tmp0, tmp1, tmp2, tmp3
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vshll.s16 \tmp0, \in0, #6
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vld1.s16 {\in0}, [r1, :64]!
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vmov \tmp1, \tmp0
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vmull.s16 \tmp2, \in1, \in0[1]
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vmull.s16 \tmp3, \in1, \in0[3]
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vmlal.s16 \tmp0, \in2, \in0[0] @e0
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vmlsl.s16 \tmp1, \in2, \in0[0] @e1
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vmlal.s16 \tmp2, \in3, \in0[3] @o0
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vmlsl.s16 \tmp3, \in3, \in0[1] @o1
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vld1.s16 {\in0}, [r1, :64]
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vadd.s32 \out0, \tmp0, \tmp2
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vadd.s32 \out1, \tmp1, \tmp3
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vsub.s32 \out2, \tmp1, \tmp3
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vsub.s32 \out3, \tmp0, \tmp2
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sub r1, r1, #8
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.endm
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@ Do a 4x4 transpose, using q registers for the subtransposes that don't
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@ need to address the indiviudal d registers.
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@ r0,r1 == rq0, r2,r3 == rq1
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.macro transpose_4x4 rq0, rq1, r0, r1, r2, r3
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vtrn.32 \rq0, \rq1
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vtrn.16 \r0, \r1
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vtrn.16 \r2, \r3
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.endm
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.macro idct_4x4 bitdepth
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function ff_hevc_idct_4x4_\bitdepth\()_neon, export=1
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@r0 - coeffs
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vld1.s16 {q0-q1}, [r0, :128]
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movrel r1, trans
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vld1.s16 {d4}, [r1, :64]
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tr_4x4 d0, d1, d2, d3, d16, d17, d18, d19, 7, q10, q11, q12, q13, q0
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transpose_4x4 q8, q9, d16, d17, d18, d19
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tr_4x4 d16, d17, d18, d19, d0, d1, d2, d3, 20 - \bitdepth, q10, q11, q12, q13, q0
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transpose_4x4 q0, q1, d0, d1, d2, d3
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vst1.s16 {d0-d3}, [r0, :128]
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bx lr
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endfunc
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.endm
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.macro transpose8_4x4 r0, r1, r2, r3
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vtrn.16 \r0, \r1
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vtrn.16 \r2, \r3
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vtrn.32 \r0, \r2
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vtrn.32 \r1, \r3
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.endm
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.macro transpose_8x8 r0, r1, r2, r3, r4, r5, r6, r7, l0, l1, l2, l3, l4, l5, l6, l7
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transpose8_4x4 \r0, \r1, \r2, \r3
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transpose8_4x4 \r4, \r5, \r6, \r7
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transpose8_4x4 \l0, \l1, \l2, \l3
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transpose8_4x4 \l4, \l5, \l6, \l7
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.endm
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.macro tr_8x4 shift, in0, in1, in2, in3, in4, in5, in6, in7
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tr_4x4_8 \in0, \in2, \in4, \in6, q8, q9, q10, q11, q12, q13, q14, q15
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vmull.s16 q14, \in1, \in0[2]
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vmull.s16 q12, \in1, \in0[0]
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vmull.s16 q13, \in1, \in0[1]
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sum_sub q14, \in3, \in0[0], -
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sum_sub q12, \in3, \in0[1], +
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sum_sub q13, \in3, \in0[3], -
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sum_sub q14, \in5, \in0[3], +
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sum_sub q12, \in5, \in0[2], +
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sum_sub q13, \in5, \in0[0], -
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sum_sub q14, \in7, \in0[1], +
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sum_sub q12, \in7, \in0[3], +
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sum_sub q13, \in7, \in0[2], -
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vadd.s32 q15, q10, q14
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vsub.s32 q10, q10, q14
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vqrshrn.s32 \in2, q15, \shift
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vmull.s16 q15, \in1, \in0[3]
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sum_sub q15, \in3, \in0[2], -
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sum_sub q15, \in5, \in0[1], +
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sum_sub q15, \in7, \in0[0], -
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vqrshrn.s32 \in5, q10, \shift
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vadd.s32 q10, q8, q12
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vsub.s32 q8, q8, q12
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vadd.s32 q12, q9, q13
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vsub.s32 q9, q9, q13
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vadd.s32 q14, q11, q15
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vsub.s32 q11, q11, q15
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vqrshrn.s32 \in0, q10, \shift
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vqrshrn.s32 \in7, q8, \shift
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vqrshrn.s32 \in1, q12, \shift
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vqrshrn.s32 \in6, q9, \shift
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vqrshrn.s32 \in3, q14, \shift
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vqrshrn.s32 \in4, q11, \shift
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.endm
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.macro idct_8x8 bitdepth
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function ff_hevc_idct_8x8_\bitdepth\()_neon, export=1
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@r0 - coeffs
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vpush {q4-q7}
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mov r1, r0
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mov r2, #64
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add r3, r0, #32
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vld1.s16 {q0-q1}, [r1,:128], r2
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vld1.s16 {q2-q3}, [r3,:128], r2
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vld1.s16 {q4-q5}, [r1,:128], r2
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vld1.s16 {q6-q7}, [r3,:128], r2
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movrel r1, trans
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tr_8x4 7, d0, d2, d4, d6, d8, d10, d12, d14
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tr_8x4 7, d1, d3, d5, d7, d9, d11, d13, d15
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@ Transpose each 4x4 block, and swap how d4-d7 and d8-d11 are used.
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@ Layout before:
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@ d0 d1
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@ d2 d3
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@ d4 d5
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@ d6 d7
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@ d8 d9
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@ d10 d11
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@ d12 d13
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@ d14 d15
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transpose_8x8 d0, d2, d4, d6, d8, d10, d12, d14, d1, d3, d5, d7, d9, d11, d13, d15
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@ Now the layout is:
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@ d0 d8
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@ d2 d10
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@ d4 d12
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@ d6 d14
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@ d1 d9
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@ d3 d11
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@ d5 d13
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@ d7 d15
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tr_8x4 20 - \bitdepth, d0, d2, d4, d6, d1, d3, d5, d7
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vswp d0, d8
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tr_8x4 20 - \bitdepth, d0, d10, d12, d14, d9, d11, d13, d15
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vswp d0, d8
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transpose_8x8 d0, d2, d4, d6, d8, d10, d12, d14, d1, d3, d5, d7, d9, d11, d13, d15
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mov r1, r0
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mov r2, #64
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add r3, r0, #32
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vst1.s16 {q0-q1}, [r1,:128], r2
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vst1.s16 {q2-q3}, [r3,:128], r2
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vst1.s16 {q4-q5}, [r1,:128], r2
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vst1.s16 {q6-q7}, [r3,:128], r2
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vpop {q4-q7}
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bx lr
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endfunc
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.endm
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idct_4x4 8
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idct_4x4 10
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idct_8x8 8
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idct_8x8 10
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