2014-11-30 01:04:37 +02:00
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/*
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2022-11-05 22:17:37 +02:00
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* H.264/HEVC/AV1 hardware encoding using nvidia nvenc
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2016-08-28 19:51:22 +02:00
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* Copyright (c) 2016 Timo Rothenpieler <timo@rothenpieler.org>
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2014-11-30 01:04:37 +02:00
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*
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* This file is part of FFmpeg.
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*
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* FFmpeg is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* FFmpeg is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with FFmpeg; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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2016-05-25 15:04:28 +02:00
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#include "config.h"
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2022-02-23 14:56:49 +02:00
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#include "config_components.h"
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2016-05-25 15:04:28 +02:00
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2016-10-10 12:55:59 +02:00
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#include "nvenc.h"
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2020-06-28 04:34:12 +02:00
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#include "hevc_sei.h"
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2022-11-05 22:18:36 +02:00
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#if CONFIG_AV1_NVENC_ENCODER
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#include "av1.h"
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#endif
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2014-11-30 01:04:37 +02:00
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2016-10-10 12:55:59 +02:00
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#include "libavutil/hwcontext_cuda.h"
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2016-05-29 14:23:26 +02:00
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#include "libavutil/hwcontext.h"
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2018-11-11 08:47:28 +02:00
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#include "libavutil/cuda_check.h"
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2014-11-30 01:04:37 +02:00
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#include "libavutil/imgutils.h"
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#include "libavutil/mem.h"
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2016-11-25 21:11:45 +02:00
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#include "libavutil/pixdesc.h"
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2022-11-10 14:05:59 +02:00
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#include "libavutil/mathematics.h"
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2020-08-09 19:01:16 +02:00
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#include "atsc_a53.h"
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2023-09-26 01:08:08 +02:00
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#include "codec_desc.h"
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2020-06-09 23:31:32 +02:00
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#include "encode.h"
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2014-11-30 01:04:37 +02:00
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#include "internal.h"
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2020-06-02 23:38:33 +02:00
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#include "packet_internal.h"
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2016-05-21 00:08:06 +02:00
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2018-11-11 08:47:28 +02:00
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#define CHECK_CU(x) FF_CUDA_CHECK_DL(avctx, dl_fn->cuda_dl, x)
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2016-05-29 14:23:26 +02:00
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#define NVENC_CAP 0x30
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2023-06-01 23:46:46 +02:00
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#ifndef NVENC_NO_DEPRECATED_RC
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2017-05-09 13:57:39 +02:00
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#define IS_CBR(rc) (rc == NV_ENC_PARAMS_RC_CBR || \
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rc == NV_ENC_PARAMS_RC_CBR_LOWDELAY_HQ || \
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rc == NV_ENC_PARAMS_RC_CBR_HQ)
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2023-06-01 23:46:46 +02:00
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#else
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#define IS_CBR(rc) (rc == NV_ENC_PARAMS_RC_CBR)
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#endif
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2016-05-25 18:39:54 +02:00
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2016-05-25 15:04:28 +02:00
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const enum AVPixelFormat ff_nvenc_pix_fmts[] = {
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AV_PIX_FMT_YUV420P,
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AV_PIX_FMT_NV12,
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2016-08-25 17:18:03 +02:00
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AV_PIX_FMT_P010,
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2016-05-25 15:04:28 +02:00
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AV_PIX_FMT_YUV444P,
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2018-02-25 19:08:06 +02:00
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AV_PIX_FMT_P016, // Truncated to 10bits
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AV_PIX_FMT_YUV444P16, // Truncated to 10bits
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2016-09-07 15:35:14 +02:00
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AV_PIX_FMT_0RGB32,
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2022-07-05 01:58:10 +02:00
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AV_PIX_FMT_RGB32,
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2016-09-07 15:35:14 +02:00
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AV_PIX_FMT_0BGR32,
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2022-07-05 01:58:10 +02:00
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AV_PIX_FMT_BGR32,
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AV_PIX_FMT_X2RGB10,
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AV_PIX_FMT_X2BGR10,
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2021-03-30 22:08:49 +02:00
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AV_PIX_FMT_GBRP,
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AV_PIX_FMT_GBRP16, // Truncated to 10bits
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2016-05-25 15:04:28 +02:00
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AV_PIX_FMT_CUDA,
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2017-11-11 17:51:58 +02:00
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#if CONFIG_D3D11VA
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AV_PIX_FMT_D3D11,
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#endif
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2016-05-25 15:04:28 +02:00
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AV_PIX_FMT_NONE
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};
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2014-11-30 01:04:37 +02:00
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2020-11-08 20:51:15 +02:00
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const AVCodecHWConfigInternal *const ff_nvenc_hw_configs[] = {
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2020-04-13 17:33:18 +02:00
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HW_CONFIG_ENCODER_FRAMES(CUDA, CUDA),
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HW_CONFIG_ENCODER_DEVICE(NONE, CUDA),
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#if CONFIG_D3D11VA
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HW_CONFIG_ENCODER_FRAMES(D3D11, D3D11VA),
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HW_CONFIG_ENCODER_DEVICE(NONE, D3D11VA),
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#endif
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NULL,
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};
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2021-03-30 22:08:49 +02:00
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#define IS_10BIT(pix_fmt) (pix_fmt == AV_PIX_FMT_P010 || \
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pix_fmt == AV_PIX_FMT_P016 || \
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pix_fmt == AV_PIX_FMT_YUV444P16 || \
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2022-11-15 00:10:20 +02:00
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pix_fmt == AV_PIX_FMT_X2RGB10 || \
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pix_fmt == AV_PIX_FMT_X2BGR10 || \
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2021-03-30 22:08:49 +02:00
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pix_fmt == AV_PIX_FMT_GBRP16)
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2016-08-25 17:18:03 +02:00
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2023-10-03 17:31:11 +02:00
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#define IS_RGB(pix_fmt) (pix_fmt == AV_PIX_FMT_0RGB32 || \
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pix_fmt == AV_PIX_FMT_RGB32 || \
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pix_fmt == AV_PIX_FMT_0BGR32 || \
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pix_fmt == AV_PIX_FMT_BGR32 || \
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pix_fmt == AV_PIX_FMT_X2RGB10 || \
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pix_fmt == AV_PIX_FMT_X2BGR10)
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2021-03-30 22:08:49 +02:00
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#define IS_YUV444(pix_fmt) (pix_fmt == AV_PIX_FMT_YUV444P || \
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pix_fmt == AV_PIX_FMT_YUV444P16 || \
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pix_fmt == AV_PIX_FMT_GBRP || \
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2023-10-03 17:31:11 +02:00
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pix_fmt == AV_PIX_FMT_GBRP16 || \
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(ctx->rgb_mode == NVENC_RGB_MODE_444 && IS_RGB(pix_fmt)))
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2021-03-30 22:08:49 +02:00
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#define IS_GBRP(pix_fmt) (pix_fmt == AV_PIX_FMT_GBRP || \
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pix_fmt == AV_PIX_FMT_GBRP16)
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2016-08-25 17:18:03 +02:00
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2016-05-20 17:37:00 +02:00
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static const struct {
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NVENCSTATUS nverr;
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int averr;
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const char *desc;
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} nvenc_errors[] = {
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{ NV_ENC_SUCCESS, 0, "success" },
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{ NV_ENC_ERR_NO_ENCODE_DEVICE, AVERROR(ENOENT), "no encode device" },
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{ NV_ENC_ERR_UNSUPPORTED_DEVICE, AVERROR(ENOSYS), "unsupported device" },
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{ NV_ENC_ERR_INVALID_ENCODERDEVICE, AVERROR(EINVAL), "invalid encoder device" },
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{ NV_ENC_ERR_INVALID_DEVICE, AVERROR(EINVAL), "invalid device" },
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{ NV_ENC_ERR_DEVICE_NOT_EXIST, AVERROR(EIO), "device does not exist" },
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{ NV_ENC_ERR_INVALID_PTR, AVERROR(EFAULT), "invalid ptr" },
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{ NV_ENC_ERR_INVALID_EVENT, AVERROR(EINVAL), "invalid event" },
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{ NV_ENC_ERR_INVALID_PARAM, AVERROR(EINVAL), "invalid param" },
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{ NV_ENC_ERR_INVALID_CALL, AVERROR(EINVAL), "invalid call" },
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{ NV_ENC_ERR_OUT_OF_MEMORY, AVERROR(ENOMEM), "out of memory" },
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{ NV_ENC_ERR_ENCODER_NOT_INITIALIZED, AVERROR(EINVAL), "encoder not initialized" },
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{ NV_ENC_ERR_UNSUPPORTED_PARAM, AVERROR(ENOSYS), "unsupported param" },
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{ NV_ENC_ERR_LOCK_BUSY, AVERROR(EAGAIN), "lock busy" },
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2016-09-24 20:31:00 +02:00
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{ NV_ENC_ERR_NOT_ENOUGH_BUFFER, AVERROR_BUFFER_TOO_SMALL, "not enough buffer"},
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2016-05-20 17:37:00 +02:00
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{ NV_ENC_ERR_INVALID_VERSION, AVERROR(EINVAL), "invalid version" },
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{ NV_ENC_ERR_MAP_FAILED, AVERROR(EIO), "map failed" },
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{ NV_ENC_ERR_NEED_MORE_INPUT, AVERROR(EAGAIN), "need more input" },
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{ NV_ENC_ERR_ENCODER_BUSY, AVERROR(EAGAIN), "encoder busy" },
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{ NV_ENC_ERR_EVENT_NOT_REGISTERD, AVERROR(EBADF), "event not registered" },
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{ NV_ENC_ERR_GENERIC, AVERROR_UNKNOWN, "generic error" },
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{ NV_ENC_ERR_INCOMPATIBLE_CLIENT_KEY, AVERROR(EINVAL), "incompatible client key" },
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{ NV_ENC_ERR_UNIMPLEMENTED, AVERROR(ENOSYS), "unimplemented" },
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{ NV_ENC_ERR_RESOURCE_REGISTER_FAILED, AVERROR(EIO), "resource register failed" },
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{ NV_ENC_ERR_RESOURCE_NOT_REGISTERED, AVERROR(EBADF), "resource not registered" },
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{ NV_ENC_ERR_RESOURCE_NOT_MAPPED, AVERROR(EBADF), "resource not mapped" },
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};
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static int nvenc_map_error(NVENCSTATUS err, const char **desc)
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{
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int i;
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for (i = 0; i < FF_ARRAY_ELEMS(nvenc_errors); i++) {
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if (nvenc_errors[i].nverr == err) {
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if (desc)
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*desc = nvenc_errors[i].desc;
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return nvenc_errors[i].averr;
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}
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}
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if (desc)
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*desc = "unknown error";
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return AVERROR_UNKNOWN;
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}
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2019-09-27 19:09:11 +02:00
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static int nvenc_print_error(AVCodecContext *avctx, NVENCSTATUS err,
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2017-03-21 00:04:28 +02:00
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const char *error_string)
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2016-05-20 17:37:00 +02:00
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{
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const char *desc;
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2019-09-27 19:09:11 +02:00
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const char *details = "(no details)";
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int ret = nvenc_map_error(err, &desc);
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#ifdef NVENC_HAVE_GETLASTERRORSTRING
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NvencContext *ctx = avctx->priv_data;
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NV_ENCODE_API_FUNCTION_LIST *p_nvenc = &ctx->nvenc_dload_funcs.nvenc_funcs;
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if (p_nvenc && ctx->nvencoder)
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details = p_nvenc->nvEncGetLastErrorString(ctx->nvencoder);
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#endif
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av_log(avctx, AV_LOG_ERROR, "%s: %s (%d): %s\n", error_string, desc, err, details);
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2016-05-20 17:37:00 +02:00
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return ret;
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}
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2021-04-18 11:17:54 +02:00
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typedef struct GUIDTuple {
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const GUID guid;
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int flags;
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} GUIDTuple;
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#define PRESET_ALIAS(alias, name, ...) \
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[PRESET_ ## alias] = { NV_ENC_PRESET_ ## name ## _GUID, __VA_ARGS__ }
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#define PRESET(name, ...) PRESET_ALIAS(name, name, __VA_ARGS__)
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static void nvenc_map_preset(NvencContext *ctx)
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{
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GUIDTuple presets[] = {
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#ifdef NVENC_HAVE_NEW_PRESETS
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PRESET(P1),
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PRESET(P2),
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PRESET(P3),
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PRESET(P4),
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PRESET(P5),
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PRESET(P6),
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PRESET(P7),
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PRESET_ALIAS(SLOW, P7, NVENC_TWO_PASSES),
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PRESET_ALIAS(MEDIUM, P4, NVENC_ONE_PASS),
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PRESET_ALIAS(FAST, P1, NVENC_ONE_PASS),
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// Compat aliases
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PRESET_ALIAS(DEFAULT, P4, NVENC_DEPRECATED_PRESET),
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PRESET_ALIAS(HP, P1, NVENC_DEPRECATED_PRESET),
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PRESET_ALIAS(HQ, P7, NVENC_DEPRECATED_PRESET),
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PRESET_ALIAS(BD, P5, NVENC_DEPRECATED_PRESET),
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PRESET_ALIAS(LOW_LATENCY_DEFAULT, P4, NVENC_DEPRECATED_PRESET | NVENC_LOWLATENCY),
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PRESET_ALIAS(LOW_LATENCY_HP, P1, NVENC_DEPRECATED_PRESET | NVENC_LOWLATENCY),
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PRESET_ALIAS(LOW_LATENCY_HQ, P7, NVENC_DEPRECATED_PRESET | NVENC_LOWLATENCY),
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PRESET_ALIAS(LOSSLESS_DEFAULT, P4, NVENC_DEPRECATED_PRESET | NVENC_LOSSLESS),
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PRESET_ALIAS(LOSSLESS_HP, P1, NVENC_DEPRECATED_PRESET | NVENC_LOSSLESS),
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#else
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PRESET(DEFAULT),
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PRESET(HP),
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PRESET(HQ),
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PRESET(BD),
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PRESET_ALIAS(SLOW, HQ, NVENC_TWO_PASSES),
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PRESET_ALIAS(MEDIUM, HQ, NVENC_ONE_PASS),
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PRESET_ALIAS(FAST, HP, NVENC_ONE_PASS),
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PRESET(LOW_LATENCY_DEFAULT, NVENC_LOWLATENCY),
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PRESET(LOW_LATENCY_HP, NVENC_LOWLATENCY),
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PRESET(LOW_LATENCY_HQ, NVENC_LOWLATENCY),
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PRESET(LOSSLESS_DEFAULT, NVENC_LOSSLESS),
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PRESET(LOSSLESS_HP, NVENC_LOSSLESS),
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#endif
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};
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GUIDTuple *t = &presets[ctx->preset];
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ctx->init_encode_params.presetGUID = t->guid;
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ctx->flags = t->flags;
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#ifdef NVENC_HAVE_NEW_PRESETS
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if (ctx->tuning_info == NV_ENC_TUNING_INFO_LOSSLESS)
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ctx->flags |= NVENC_LOSSLESS;
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#endif
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}
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#undef PRESET
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#undef PRESET_ALIAS
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2017-06-01 11:55:25 +02:00
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static void nvenc_print_driver_requirement(AVCodecContext *avctx, int level)
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{
|
2024-03-31 21:43:01 +02:00
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#if NVENCAPI_CHECK_VERSION(12, 3)
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2019-09-23 15:47:27 +02:00
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const char *minver = "(unknown)";
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2024-03-31 21:43:01 +02:00
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#elif NVENCAPI_CHECK_VERSION(12, 2)
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# if defined(_WIN32) || defined(__CYGWIN__)
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const char *minver = "551.76";
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# else
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const char *minver = "550.54.14";
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# endif
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#elif NVENCAPI_CHECK_VERSION(12, 1)
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# if defined(_WIN32) || defined(__CYGWIN__)
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const char *minver = "531.61";
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# else
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const char *minver = "530.41.03";
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# endif
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2022-11-05 22:17:37 +02:00
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#elif NVENCAPI_CHECK_VERSION(12, 0)
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# if defined(_WIN32) || defined(__CYGWIN__)
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const char *minver = "522.25";
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# else
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const char *minver = "520.56.06";
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# endif
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2021-08-08 02:00:38 +02:00
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#elif NVENCAPI_CHECK_VERSION(11, 1)
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# if defined(_WIN32) || defined(__CYGWIN__)
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const char *minver = "471.41";
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# else
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const char *minver = "470.57.02";
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|
# endif
|
2020-10-17 23:10:42 +02:00
|
|
|
#elif NVENCAPI_CHECK_VERSION(11, 0)
|
|
|
|
# if defined(_WIN32) || defined(__CYGWIN__)
|
|
|
|
const char *minver = "456.71";
|
|
|
|
# else
|
|
|
|
const char *minver = "455.28";
|
|
|
|
# endif
|
2020-03-19 10:35:29 +02:00
|
|
|
#elif NVENCAPI_CHECK_VERSION(10, 0)
|
|
|
|
# if defined(_WIN32) || defined(__CYGWIN__)
|
|
|
|
const char *minver = "450.51";
|
|
|
|
# else
|
|
|
|
const char *minver = "445.87";
|
|
|
|
# endif
|
2019-09-23 15:47:27 +02:00
|
|
|
#elif NVENCAPI_CHECK_VERSION(9, 1)
|
|
|
|
# if defined(_WIN32) || defined(__CYGWIN__)
|
2019-09-24 12:00:00 +02:00
|
|
|
const char *minver = "436.15";
|
2019-09-23 15:47:27 +02:00
|
|
|
# else
|
|
|
|
const char *minver = "435.21";
|
|
|
|
# endif
|
|
|
|
#elif NVENCAPI_CHECK_VERSION(9, 0)
|
2019-03-10 01:25:31 +02:00
|
|
|
# if defined(_WIN32) || defined(__CYGWIN__)
|
|
|
|
const char *minver = "418.81";
|
|
|
|
# else
|
|
|
|
const char *minver = "418.30";
|
|
|
|
# endif
|
|
|
|
#elif NVENCAPI_CHECK_VERSION(8, 2)
|
|
|
|
# if defined(_WIN32) || defined(__CYGWIN__)
|
|
|
|
const char *minver = "397.93";
|
|
|
|
# else
|
|
|
|
const char *minver = "396.24";
|
|
|
|
#endif
|
|
|
|
#elif NVENCAPI_CHECK_VERSION(8, 1)
|
2018-04-11 14:28:36 +02:00
|
|
|
# if defined(_WIN32) || defined(__CYGWIN__)
|
|
|
|
const char *minver = "390.77";
|
|
|
|
# else
|
|
|
|
const char *minver = "390.25";
|
|
|
|
# endif
|
2017-06-01 11:55:25 +02:00
|
|
|
#else
|
2018-04-11 14:28:36 +02:00
|
|
|
# if defined(_WIN32) || defined(__CYGWIN__)
|
|
|
|
const char *minver = "378.66";
|
|
|
|
# else
|
2017-06-01 11:55:25 +02:00
|
|
|
const char *minver = "378.13";
|
2018-04-11 14:28:36 +02:00
|
|
|
# endif
|
2017-06-01 11:55:25 +02:00
|
|
|
#endif
|
|
|
|
av_log(avctx, level, "The minimum required Nvidia driver for nvenc is %s or newer\n", minver);
|
|
|
|
}
|
|
|
|
|
2016-05-29 14:23:26 +02:00
|
|
|
static av_cold int nvenc_load_libraries(AVCodecContext *avctx)
|
2014-11-30 01:04:37 +02:00
|
|
|
{
|
2017-03-21 00:04:28 +02:00
|
|
|
NvencContext *ctx = avctx->priv_data;
|
2014-11-30 01:04:37 +02:00
|
|
|
NvencDynLoadFunctions *dl_fn = &ctx->nvenc_dload_funcs;
|
2016-05-29 14:23:26 +02:00
|
|
|
NVENCSTATUS err;
|
2016-08-28 19:46:44 +02:00
|
|
|
uint32_t nvenc_max_ver;
|
2016-10-10 12:55:59 +02:00
|
|
|
int ret;
|
|
|
|
|
2017-11-18 19:16:14 +02:00
|
|
|
ret = cuda_load_functions(&dl_fn->cuda_dl, avctx);
|
2016-10-10 12:55:59 +02:00
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
|
2017-11-18 19:16:14 +02:00
|
|
|
ret = nvenc_load_functions(&dl_fn->nvenc_dl, avctx);
|
2017-06-01 11:55:25 +02:00
|
|
|
if (ret < 0) {
|
|
|
|
nvenc_print_driver_requirement(avctx, AV_LOG_ERROR);
|
2016-10-10 12:55:59 +02:00
|
|
|
return ret;
|
2017-06-01 11:55:25 +02:00
|
|
|
}
|
2014-11-30 01:04:37 +02:00
|
|
|
|
2016-10-10 12:55:59 +02:00
|
|
|
err = dl_fn->nvenc_dl->NvEncodeAPIGetMaxSupportedVersion(&nvenc_max_ver);
|
2016-08-28 19:46:44 +02:00
|
|
|
if (err != NV_ENC_SUCCESS)
|
|
|
|
return nvenc_print_error(avctx, err, "Failed to query nvenc max version");
|
|
|
|
|
|
|
|
av_log(avctx, AV_LOG_VERBOSE, "Loaded Nvenc version %d.%d\n", nvenc_max_ver >> 4, nvenc_max_ver & 0xf);
|
|
|
|
|
|
|
|
if ((NVENCAPI_MAJOR_VERSION << 4 | NVENCAPI_MINOR_VERSION) > nvenc_max_ver) {
|
|
|
|
av_log(avctx, AV_LOG_ERROR, "Driver does not support the required nvenc API version. "
|
|
|
|
"Required: %d.%d Found: %d.%d\n",
|
|
|
|
NVENCAPI_MAJOR_VERSION, NVENCAPI_MINOR_VERSION,
|
|
|
|
nvenc_max_ver >> 4, nvenc_max_ver & 0xf);
|
2017-06-01 11:55:25 +02:00
|
|
|
nvenc_print_driver_requirement(avctx, AV_LOG_ERROR);
|
2016-08-28 19:46:44 +02:00
|
|
|
return AVERROR(ENOSYS);
|
|
|
|
}
|
|
|
|
|
2016-05-29 14:23:26 +02:00
|
|
|
dl_fn->nvenc_funcs.version = NV_ENCODE_API_FUNCTION_LIST_VER;
|
2014-11-30 01:04:37 +02:00
|
|
|
|
2016-10-10 12:55:59 +02:00
|
|
|
err = dl_fn->nvenc_dl->NvEncodeAPICreateInstance(&dl_fn->nvenc_funcs);
|
2016-05-29 14:23:26 +02:00
|
|
|
if (err != NV_ENC_SUCCESS)
|
|
|
|
return nvenc_print_error(avctx, err, "Failed to create nvenc instance");
|
2014-11-30 01:04:37 +02:00
|
|
|
|
2016-05-29 14:23:26 +02:00
|
|
|
av_log(avctx, AV_LOG_VERBOSE, "Nvenc initialized successfully\n");
|
2014-11-30 01:04:37 +02:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2017-11-11 17:13:24 +02:00
|
|
|
static int nvenc_push_context(AVCodecContext *avctx)
|
|
|
|
{
|
|
|
|
NvencContext *ctx = avctx->priv_data;
|
|
|
|
NvencDynLoadFunctions *dl_fn = &ctx->nvenc_dload_funcs;
|
|
|
|
|
2017-11-11 17:51:58 +02:00
|
|
|
if (ctx->d3d11_device)
|
|
|
|
return 0;
|
|
|
|
|
2018-11-11 08:47:28 +02:00
|
|
|
return CHECK_CU(dl_fn->cuda_dl->cuCtxPushCurrent(ctx->cu_context));
|
2017-11-11 17:13:24 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
static int nvenc_pop_context(AVCodecContext *avctx)
|
|
|
|
{
|
|
|
|
NvencContext *ctx = avctx->priv_data;
|
|
|
|
NvencDynLoadFunctions *dl_fn = &ctx->nvenc_dload_funcs;
|
|
|
|
CUcontext dummy;
|
|
|
|
|
2017-11-11 17:51:58 +02:00
|
|
|
if (ctx->d3d11_device)
|
|
|
|
return 0;
|
|
|
|
|
2018-11-11 08:47:28 +02:00
|
|
|
return CHECK_CU(dl_fn->cuda_dl->cuCtxPopCurrent(&dummy));
|
2017-11-11 17:13:24 +02:00
|
|
|
}
|
|
|
|
|
2016-05-29 14:23:26 +02:00
|
|
|
static av_cold int nvenc_open_session(AVCodecContext *avctx)
|
2014-11-30 01:04:37 +02:00
|
|
|
{
|
2016-05-29 14:23:26 +02:00
|
|
|
NV_ENC_OPEN_ENCODE_SESSION_EX_PARAMS params = { 0 };
|
|
|
|
NvencContext *ctx = avctx->priv_data;
|
|
|
|
NV_ENCODE_API_FUNCTION_LIST *p_nvenc = &ctx->nvenc_dload_funcs.nvenc_funcs;
|
|
|
|
NVENCSTATUS ret;
|
|
|
|
|
|
|
|
params.version = NV_ENC_OPEN_ENCODE_SESSION_EX_PARAMS_VER;
|
|
|
|
params.apiVersion = NVENCAPI_VERSION;
|
2017-11-11 17:51:58 +02:00
|
|
|
if (ctx->d3d11_device) {
|
|
|
|
params.device = ctx->d3d11_device;
|
|
|
|
params.deviceType = NV_ENC_DEVICE_TYPE_DIRECTX;
|
|
|
|
} else {
|
|
|
|
params.device = ctx->cu_context;
|
|
|
|
params.deviceType = NV_ENC_DEVICE_TYPE_CUDA;
|
|
|
|
}
|
2016-05-29 14:23:26 +02:00
|
|
|
|
|
|
|
ret = p_nvenc->nvEncOpenEncodeSessionEx(¶ms, &ctx->nvencoder);
|
|
|
|
if (ret != NV_ENC_SUCCESS) {
|
|
|
|
ctx->nvencoder = NULL;
|
|
|
|
return nvenc_print_error(avctx, ret, "OpenEncodeSessionEx failed");
|
2014-11-30 01:04:37 +02:00
|
|
|
}
|
2016-05-29 14:23:26 +02:00
|
|
|
|
|
|
|
return 0;
|
2014-11-30 01:04:37 +02:00
|
|
|
}
|
|
|
|
|
2016-05-29 14:23:26 +02:00
|
|
|
static int nvenc_check_codec_support(AVCodecContext *avctx)
|
2014-11-30 01:04:37 +02:00
|
|
|
{
|
2017-03-21 00:04:28 +02:00
|
|
|
NvencContext *ctx = avctx->priv_data;
|
2016-05-29 14:23:26 +02:00
|
|
|
NV_ENCODE_API_FUNCTION_LIST *p_nvenc = &ctx->nvenc_dload_funcs.nvenc_funcs;
|
|
|
|
int i, ret, count = 0;
|
|
|
|
GUID *guids = NULL;
|
2014-11-30 01:04:37 +02:00
|
|
|
|
2016-05-29 14:23:26 +02:00
|
|
|
ret = p_nvenc->nvEncGetEncodeGUIDCount(ctx->nvencoder, &count);
|
2015-03-24 06:34:59 +02:00
|
|
|
|
2016-05-29 14:23:26 +02:00
|
|
|
if (ret != NV_ENC_SUCCESS || !count)
|
|
|
|
return AVERROR(ENOSYS);
|
2016-05-25 12:15:03 +02:00
|
|
|
|
2016-05-29 14:23:26 +02:00
|
|
|
guids = av_malloc(count * sizeof(GUID));
|
|
|
|
if (!guids)
|
|
|
|
return AVERROR(ENOMEM);
|
2014-11-30 01:04:37 +02:00
|
|
|
|
2016-05-29 14:23:26 +02:00
|
|
|
ret = p_nvenc->nvEncGetEncodeGUIDs(ctx->nvencoder, guids, count, &count);
|
|
|
|
if (ret != NV_ENC_SUCCESS) {
|
|
|
|
ret = AVERROR(ENOSYS);
|
|
|
|
goto fail;
|
|
|
|
}
|
2014-11-30 01:04:37 +02:00
|
|
|
|
2016-05-29 14:23:26 +02:00
|
|
|
ret = AVERROR(ENOSYS);
|
|
|
|
for (i = 0; i < count; i++) {
|
|
|
|
if (!memcmp(&guids[i], &ctx->init_encode_params.encodeGUID, sizeof(*guids))) {
|
|
|
|
ret = 0;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
2014-11-30 01:04:37 +02:00
|
|
|
|
2016-05-29 14:23:26 +02:00
|
|
|
fail:
|
|
|
|
av_free(guids);
|
2014-11-30 01:04:37 +02:00
|
|
|
|
2016-05-29 14:23:26 +02:00
|
|
|
return ret;
|
|
|
|
}
|
2014-11-30 01:04:37 +02:00
|
|
|
|
2016-05-29 14:23:26 +02:00
|
|
|
static int nvenc_check_cap(AVCodecContext *avctx, NV_ENC_CAPS cap)
|
|
|
|
{
|
|
|
|
NvencContext *ctx = avctx->priv_data;
|
|
|
|
NV_ENCODE_API_FUNCTION_LIST *p_nvenc = &ctx->nvenc_dload_funcs.nvenc_funcs;
|
|
|
|
NV_ENC_CAPS_PARAM params = { 0 };
|
|
|
|
int ret, val = 0;
|
2014-11-30 01:04:37 +02:00
|
|
|
|
2016-05-29 14:23:26 +02:00
|
|
|
params.version = NV_ENC_CAPS_PARAM_VER;
|
|
|
|
params.capsToQuery = cap;
|
2014-11-30 01:04:37 +02:00
|
|
|
|
2016-05-29 14:23:26 +02:00
|
|
|
ret = p_nvenc->nvEncGetEncodeCaps(ctx->nvencoder, ctx->init_encode_params.encodeGUID, ¶ms, &val);
|
2014-11-30 01:04:37 +02:00
|
|
|
|
2016-05-29 14:23:26 +02:00
|
|
|
if (ret == NV_ENC_SUCCESS)
|
|
|
|
return val;
|
|
|
|
return 0;
|
|
|
|
}
|
2014-11-30 01:04:37 +02:00
|
|
|
|
2016-05-29 14:23:26 +02:00
|
|
|
static int nvenc_check_capabilities(AVCodecContext *avctx)
|
|
|
|
{
|
|
|
|
NvencContext *ctx = avctx->priv_data;
|
2023-03-10 14:09:10 +02:00
|
|
|
int tmp, ret;
|
2014-11-30 01:04:37 +02:00
|
|
|
|
2016-05-29 14:23:26 +02:00
|
|
|
ret = nvenc_check_codec_support(avctx);
|
|
|
|
if (ret < 0) {
|
2019-10-27 04:30:54 +02:00
|
|
|
av_log(avctx, AV_LOG_WARNING, "Codec not supported\n");
|
2016-05-29 14:23:26 +02:00
|
|
|
return ret;
|
2014-11-30 01:04:37 +02:00
|
|
|
}
|
|
|
|
|
2016-05-29 14:23:26 +02:00
|
|
|
ret = nvenc_check_cap(avctx, NV_ENC_CAPS_SUPPORT_YUV444_ENCODE);
|
2016-08-25 17:18:03 +02:00
|
|
|
if (IS_YUV444(ctx->data_pix_fmt) && ret <= 0) {
|
2019-10-27 04:30:54 +02:00
|
|
|
av_log(avctx, AV_LOG_WARNING, "YUV444P not supported\n");
|
2016-05-29 14:23:26 +02:00
|
|
|
return AVERROR(ENOSYS);
|
2014-11-30 01:04:37 +02:00
|
|
|
}
|
|
|
|
|
2016-05-29 14:23:26 +02:00
|
|
|
ret = nvenc_check_cap(avctx, NV_ENC_CAPS_SUPPORT_LOSSLESS_ENCODE);
|
2021-04-18 11:17:54 +02:00
|
|
|
if (ctx->flags & NVENC_LOSSLESS && ret <= 0) {
|
2019-10-27 04:30:54 +02:00
|
|
|
av_log(avctx, AV_LOG_WARNING, "Lossless encoding not supported\n");
|
2016-05-29 14:23:26 +02:00
|
|
|
return AVERROR(ENOSYS);
|
|
|
|
}
|
2014-11-30 01:04:37 +02:00
|
|
|
|
2016-05-29 14:23:26 +02:00
|
|
|
ret = nvenc_check_cap(avctx, NV_ENC_CAPS_WIDTH_MAX);
|
|
|
|
if (ret < avctx->width) {
|
2019-10-27 04:30:54 +02:00
|
|
|
av_log(avctx, AV_LOG_WARNING, "Width %d exceeds %d\n",
|
2016-05-29 14:23:26 +02:00
|
|
|
avctx->width, ret);
|
|
|
|
return AVERROR(ENOSYS);
|
|
|
|
}
|
2014-11-30 01:04:37 +02:00
|
|
|
|
2016-05-29 14:23:26 +02:00
|
|
|
ret = nvenc_check_cap(avctx, NV_ENC_CAPS_HEIGHT_MAX);
|
|
|
|
if (ret < avctx->height) {
|
2019-10-27 04:30:54 +02:00
|
|
|
av_log(avctx, AV_LOG_WARNING, "Height %d exceeds %d\n",
|
2016-05-29 14:23:26 +02:00
|
|
|
avctx->height, ret);
|
|
|
|
return AVERROR(ENOSYS);
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = nvenc_check_cap(avctx, NV_ENC_CAPS_NUM_MAX_BFRAMES);
|
|
|
|
if (ret < avctx->max_b_frames) {
|
2019-10-27 04:30:54 +02:00
|
|
|
av_log(avctx, AV_LOG_WARNING, "Max B-frames %d exceed %d\n",
|
2016-05-29 14:23:26 +02:00
|
|
|
avctx->max_b_frames, ret);
|
|
|
|
|
|
|
|
return AVERROR(ENOSYS);
|
|
|
|
}
|
2014-11-30 01:04:37 +02:00
|
|
|
|
2016-06-06 21:19:29 +02:00
|
|
|
ret = nvenc_check_cap(avctx, NV_ENC_CAPS_SUPPORT_FIELD_ENCODING);
|
|
|
|
if (ret < 1 && avctx->flags & AV_CODEC_FLAG_INTERLACED_DCT) {
|
2019-10-27 04:30:54 +02:00
|
|
|
av_log(avctx, AV_LOG_WARNING,
|
2016-06-06 21:19:29 +02:00
|
|
|
"Interlaced encoding is not supported. Supported level: %d\n",
|
|
|
|
ret);
|
|
|
|
return AVERROR(ENOSYS);
|
|
|
|
}
|
|
|
|
|
2016-08-25 17:18:03 +02:00
|
|
|
ret = nvenc_check_cap(avctx, NV_ENC_CAPS_SUPPORT_10BIT_ENCODE);
|
2024-04-19 10:38:51 +02:00
|
|
|
if ((IS_10BIT(ctx->data_pix_fmt) || ctx->highbitdepth) && ret <= 0) {
|
2019-10-27 04:30:54 +02:00
|
|
|
av_log(avctx, AV_LOG_WARNING, "10 bit encode not supported\n");
|
2016-08-25 17:18:03 +02:00
|
|
|
return AVERROR(ENOSYS);
|
|
|
|
}
|
|
|
|
|
2016-08-25 17:20:03 +02:00
|
|
|
ret = nvenc_check_cap(avctx, NV_ENC_CAPS_SUPPORT_LOOKAHEAD);
|
|
|
|
if (ctx->rc_lookahead > 0 && ret <= 0) {
|
2019-10-27 04:30:54 +02:00
|
|
|
av_log(avctx, AV_LOG_WARNING, "RC lookahead not supported\n");
|
2016-08-25 17:20:03 +02:00
|
|
|
return AVERROR(ENOSYS);
|
|
|
|
}
|
|
|
|
|
2016-10-14 17:02:54 +02:00
|
|
|
ret = nvenc_check_cap(avctx, NV_ENC_CAPS_SUPPORT_TEMPORAL_AQ);
|
|
|
|
if (ctx->temporal_aq > 0 && ret <= 0) {
|
2019-10-27 04:30:54 +02:00
|
|
|
av_log(avctx, AV_LOG_WARNING, "Temporal AQ not supported\n");
|
2016-10-14 17:02:54 +02:00
|
|
|
return AVERROR(ENOSYS);
|
|
|
|
}
|
|
|
|
|
2017-05-09 16:24:54 +02:00
|
|
|
ret = nvenc_check_cap(avctx, NV_ENC_CAPS_SUPPORT_WEIGHTED_PREDICTION);
|
|
|
|
if (ctx->weighted_pred > 0 && ret <= 0) {
|
2019-10-27 04:30:54 +02:00
|
|
|
av_log (avctx, AV_LOG_WARNING, "Weighted Prediction not supported\n");
|
2017-05-09 16:24:54 +02:00
|
|
|
return AVERROR(ENOSYS);
|
|
|
|
}
|
|
|
|
|
2017-08-30 21:06:25 +02:00
|
|
|
ret = nvenc_check_cap(avctx, NV_ENC_CAPS_SUPPORT_CABAC);
|
|
|
|
if (ctx->coder == NV_ENC_H264_ENTROPY_CODING_MODE_CABAC && ret <= 0) {
|
2019-10-27 04:30:54 +02:00
|
|
|
av_log(avctx, AV_LOG_WARNING, "CABAC entropy coding not supported\n");
|
2017-08-30 21:06:25 +02:00
|
|
|
return AVERROR(ENOSYS);
|
|
|
|
}
|
|
|
|
|
2018-04-11 14:22:20 +02:00
|
|
|
#ifdef NVENC_HAVE_BFRAME_REF_MODE
|
2023-03-10 14:09:10 +02:00
|
|
|
tmp = (ctx->b_ref_mode >= 0) ? ctx->b_ref_mode : NV_ENC_BFRAME_REF_MODE_DISABLED;
|
2018-04-11 14:22:20 +02:00
|
|
|
ret = nvenc_check_cap(avctx, NV_ENC_CAPS_SUPPORT_BFRAME_REF_MODE);
|
2023-03-10 14:09:10 +02:00
|
|
|
if (tmp == NV_ENC_BFRAME_REF_MODE_EACH && ret != 1 && ret != 3) {
|
2019-10-27 04:30:54 +02:00
|
|
|
av_log(avctx, AV_LOG_WARNING, "Each B frame as reference is not supported\n");
|
2018-04-11 14:22:20 +02:00
|
|
|
return AVERROR(ENOSYS);
|
2023-03-10 14:09:10 +02:00
|
|
|
} else if (tmp != NV_ENC_BFRAME_REF_MODE_DISABLED && ret == 0) {
|
2019-10-27 04:30:54 +02:00
|
|
|
av_log(avctx, AV_LOG_WARNING, "B frames as references are not supported\n");
|
2018-04-11 14:22:20 +02:00
|
|
|
return AVERROR(ENOSYS);
|
|
|
|
}
|
|
|
|
#else
|
2023-03-10 14:09:10 +02:00
|
|
|
tmp = (ctx->b_ref_mode >= 0) ? ctx->b_ref_mode : 0;
|
|
|
|
if (tmp > 0) {
|
2019-10-27 04:30:54 +02:00
|
|
|
av_log(avctx, AV_LOG_WARNING, "B frames as references need SDK 8.1 at build time\n");
|
2018-04-11 14:22:20 +02:00
|
|
|
return AVERROR(ENOSYS);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2019-09-27 17:56:11 +02:00
|
|
|
#ifdef NVENC_HAVE_MULTIPLE_REF_FRAMES
|
|
|
|
ret = nvenc_check_cap(avctx, NV_ENC_CAPS_SUPPORT_MULTIPLE_REF_FRAMES);
|
|
|
|
if(avctx->refs != NV_ENC_NUM_REF_FRAMES_AUTOSELECT && ret <= 0) {
|
2019-10-27 04:30:54 +02:00
|
|
|
av_log(avctx, AV_LOG_WARNING, "Multiple reference frames are not supported by the device\n");
|
2019-09-27 17:56:11 +02:00
|
|
|
return AVERROR(ENOSYS);
|
|
|
|
}
|
|
|
|
#else
|
|
|
|
if(avctx->refs != 0) {
|
2019-10-27 04:30:54 +02:00
|
|
|
av_log(avctx, AV_LOG_WARNING, "Multiple reference frames need SDK 9.1 at build time\n");
|
2019-09-27 17:56:11 +02:00
|
|
|
return AVERROR(ENOSYS);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2021-09-02 12:38:57 +02:00
|
|
|
#ifdef NVENC_HAVE_SINGLE_SLICE_INTRA_REFRESH
|
|
|
|
ret = nvenc_check_cap(avctx, NV_ENC_CAPS_SINGLE_SLICE_INTRA_REFRESH);
|
|
|
|
if(ctx->single_slice_intra_refresh && ret <= 0) {
|
|
|
|
av_log(avctx, AV_LOG_WARNING, "Single slice intra refresh not supported by the device\n");
|
|
|
|
return AVERROR(ENOSYS);
|
|
|
|
}
|
|
|
|
#else
|
|
|
|
if(ctx->single_slice_intra_refresh) {
|
|
|
|
av_log(avctx, AV_LOG_WARNING, "Single slice intra refresh needs SDK 11.1 at build time\n");
|
|
|
|
return AVERROR(ENOSYS);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2021-09-06 04:01:58 +02:00
|
|
|
ret = nvenc_check_cap(avctx, NV_ENC_CAPS_SUPPORT_INTRA_REFRESH);
|
2021-09-02 12:38:57 +02:00
|
|
|
if((ctx->intra_refresh || ctx->single_slice_intra_refresh) && ret <= 0) {
|
2021-09-06 04:01:58 +02:00
|
|
|
av_log(avctx, AV_LOG_WARNING, "Intra refresh not supported by the device\n");
|
|
|
|
return AVERROR(ENOSYS);
|
|
|
|
}
|
|
|
|
|
2021-09-02 12:38:58 +02:00
|
|
|
#ifndef NVENC_HAVE_HEVC_CONSTRAINED_ENCODING
|
|
|
|
if (ctx->constrained_encoding && avctx->codec->id == AV_CODEC_ID_HEVC) {
|
|
|
|
av_log(avctx, AV_LOG_WARNING, "HEVC constrained encoding needs SDK 10.0 at build time\n");
|
|
|
|
return AVERROR(ENOSYS);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
ret = nvenc_check_cap(avctx, NV_ENC_CAPS_SUPPORT_CONSTRAINED_ENCODING);
|
|
|
|
if(ctx->constrained_encoding && ret <= 0) {
|
|
|
|
av_log(avctx, AV_LOG_WARNING, "Constrained encoding not supported by the device\n");
|
|
|
|
return AVERROR(ENOSYS);
|
|
|
|
}
|
|
|
|
|
2024-03-31 20:10:45 +02:00
|
|
|
#ifdef NVENC_HAVE_TEMPORAL_FILTER
|
|
|
|
ret = nvenc_check_cap(avctx, NV_ENC_CAPS_SUPPORT_TEMPORAL_FILTER);
|
|
|
|
if(ctx->tf_level > 0 && ret <= 0) {
|
|
|
|
av_log(avctx, AV_LOG_WARNING, "Temporal filtering not supported by the device\n");
|
|
|
|
return AVERROR(ENOSYS);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2024-03-31 20:52:27 +02:00
|
|
|
#ifdef NVENC_HAVE_LOOKAHEAD_LEVEL
|
|
|
|
ret = nvenc_check_cap(avctx, NV_ENC_CAPS_SUPPORT_LOOKAHEAD_LEVEL);
|
|
|
|
if(ctx->rc_lookahead > 0 && ctx->lookahead_level > 0 &&
|
|
|
|
ctx->lookahead_level != NV_ENC_LOOKAHEAD_LEVEL_AUTOSELECT &&
|
|
|
|
ctx->lookahead_level > ret)
|
|
|
|
{
|
|
|
|
av_log(avctx, AV_LOG_WARNING, "Lookahead level not supported. Maximum level: %d\n", ret);
|
|
|
|
return AVERROR(ENOSYS);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2024-03-31 21:26:15 +02:00
|
|
|
#ifdef NVENC_HAVE_UNIDIR_B
|
|
|
|
ret = nvenc_check_cap(avctx, NV_ENC_CAPS_SUPPORT_UNIDIRECTIONAL_B);
|
|
|
|
if(ctx->unidir_b && ret <= 0) {
|
|
|
|
av_log(avctx, AV_LOG_WARNING, "Unidirectional B-Frames not supported by the device\n");
|
|
|
|
return AVERROR(ENOSYS);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2018-05-03 02:15:52 +02:00
|
|
|
ctx->support_dyn_bitrate = nvenc_check_cap(avctx, NV_ENC_CAPS_SUPPORT_DYN_BITRATE_CHANGE);
|
|
|
|
|
2014-11-30 01:04:37 +02:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2016-05-29 14:23:26 +02:00
|
|
|
static av_cold int nvenc_check_device(AVCodecContext *avctx, int idx)
|
2014-11-30 01:04:37 +02:00
|
|
|
{
|
|
|
|
NvencContext *ctx = avctx->priv_data;
|
|
|
|
NvencDynLoadFunctions *dl_fn = &ctx->nvenc_dload_funcs;
|
2016-05-29 14:23:26 +02:00
|
|
|
NV_ENCODE_API_FUNCTION_LIST *p_nvenc = &dl_fn->nvenc_funcs;
|
|
|
|
char name[128] = { 0};
|
|
|
|
int major, minor, ret;
|
|
|
|
CUdevice cu_device;
|
|
|
|
int loglevel = AV_LOG_VERBOSE;
|
2014-11-30 01:04:37 +02:00
|
|
|
|
2016-05-29 14:23:26 +02:00
|
|
|
if (ctx->device == LIST_DEVICES)
|
|
|
|
loglevel = AV_LOG_INFO;
|
2014-11-30 01:04:37 +02:00
|
|
|
|
2018-11-11 08:47:28 +02:00
|
|
|
ret = CHECK_CU(dl_fn->cuda_dl->cuDeviceGet(&cu_device, idx));
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
2014-11-30 01:04:37 +02:00
|
|
|
|
2018-11-11 08:47:28 +02:00
|
|
|
ret = CHECK_CU(dl_fn->cuda_dl->cuDeviceGetName(name, sizeof(name), cu_device));
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
2016-05-29 14:23:26 +02:00
|
|
|
|
2018-11-11 08:47:28 +02:00
|
|
|
ret = CHECK_CU(dl_fn->cuda_dl->cuDeviceComputeCapability(&major, &minor, cu_device));
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
2016-05-29 14:23:26 +02:00
|
|
|
|
|
|
|
av_log(avctx, loglevel, "[ GPU #%d - < %s > has Compute SM %d.%d ]\n", idx, name, major, minor);
|
|
|
|
if (((major << 4) | minor) < NVENC_CAP) {
|
|
|
|
av_log(avctx, loglevel, "does not support NVENC\n");
|
|
|
|
goto fail;
|
2014-11-30 01:04:37 +02:00
|
|
|
}
|
|
|
|
|
2017-01-19 00:01:28 +02:00
|
|
|
if (ctx->device != idx && ctx->device != ANY_DEVICE)
|
|
|
|
return -1;
|
|
|
|
|
2018-11-11 08:47:28 +02:00
|
|
|
ret = CHECK_CU(dl_fn->cuda_dl->cuCtxCreate(&ctx->cu_context_internal, 0, cu_device));
|
|
|
|
if (ret < 0)
|
2016-05-29 14:23:26 +02:00
|
|
|
goto fail;
|
2014-11-30 01:04:37 +02:00
|
|
|
|
2016-05-29 14:23:26 +02:00
|
|
|
ctx->cu_context = ctx->cu_context_internal;
|
2019-09-27 18:30:10 +02:00
|
|
|
ctx->cu_stream = NULL;
|
2014-11-30 01:04:37 +02:00
|
|
|
|
2017-11-11 17:13:24 +02:00
|
|
|
if ((ret = nvenc_pop_context(avctx)) < 0)
|
2016-05-29 14:23:26 +02:00
|
|
|
goto fail2;
|
2014-11-30 01:04:37 +02:00
|
|
|
|
2016-05-29 14:23:26 +02:00
|
|
|
if ((ret = nvenc_open_session(avctx)) < 0)
|
|
|
|
goto fail2;
|
2014-11-30 01:04:37 +02:00
|
|
|
|
2016-05-29 14:23:26 +02:00
|
|
|
if ((ret = nvenc_check_capabilities(avctx)) < 0)
|
|
|
|
goto fail3;
|
2014-11-30 01:04:37 +02:00
|
|
|
|
2016-05-29 14:23:26 +02:00
|
|
|
av_log(avctx, loglevel, "supports NVENC\n");
|
2014-11-30 01:04:37 +02:00
|
|
|
|
2016-05-29 14:23:26 +02:00
|
|
|
dl_fn->nvenc_device_count++;
|
2014-11-30 01:04:37 +02:00
|
|
|
|
2017-01-19 00:01:28 +02:00
|
|
|
if (ctx->device == idx || ctx->device == ANY_DEVICE)
|
2016-05-29 14:23:26 +02:00
|
|
|
return 0;
|
2014-11-30 01:04:37 +02:00
|
|
|
|
2016-05-29 14:23:26 +02:00
|
|
|
fail3:
|
2017-11-11 17:13:24 +02:00
|
|
|
if ((ret = nvenc_push_context(avctx)) < 0)
|
|
|
|
return ret;
|
2017-05-31 04:03:14 +02:00
|
|
|
|
2016-05-29 14:23:26 +02:00
|
|
|
p_nvenc->nvEncDestroyEncoder(ctx->nvencoder);
|
|
|
|
ctx->nvencoder = NULL;
|
2014-11-30 01:04:37 +02:00
|
|
|
|
2017-11-11 17:13:24 +02:00
|
|
|
if ((ret = nvenc_pop_context(avctx)) < 0)
|
|
|
|
return ret;
|
2017-05-31 04:03:14 +02:00
|
|
|
|
2016-05-29 14:23:26 +02:00
|
|
|
fail2:
|
2018-11-11 08:47:28 +02:00
|
|
|
CHECK_CU(dl_fn->cuda_dl->cuCtxDestroy(ctx->cu_context_internal));
|
2016-05-29 14:23:26 +02:00
|
|
|
ctx->cu_context_internal = NULL;
|
2014-11-30 01:04:37 +02:00
|
|
|
|
2016-05-29 14:23:26 +02:00
|
|
|
fail:
|
|
|
|
return AVERROR(ENOSYS);
|
2014-11-30 01:04:37 +02:00
|
|
|
}
|
|
|
|
|
2016-05-20 16:49:24 +02:00
|
|
|
static av_cold int nvenc_setup_device(AVCodecContext *avctx)
|
2014-11-30 01:04:37 +02:00
|
|
|
{
|
2017-03-21 00:04:28 +02:00
|
|
|
NvencContext *ctx = avctx->priv_data;
|
2014-11-30 01:04:37 +02:00
|
|
|
NvencDynLoadFunctions *dl_fn = &ctx->nvenc_dload_funcs;
|
|
|
|
|
2016-05-25 16:05:50 +02:00
|
|
|
switch (avctx->codec->id) {
|
|
|
|
case AV_CODEC_ID_H264:
|
|
|
|
ctx->init_encode_params.encodeGUID = NV_ENC_CODEC_H264_GUID;
|
|
|
|
break;
|
|
|
|
case AV_CODEC_ID_HEVC:
|
|
|
|
ctx->init_encode_params.encodeGUID = NV_ENC_CODEC_HEVC_GUID;
|
|
|
|
break;
|
2022-11-05 22:17:37 +02:00
|
|
|
#if CONFIG_AV1_NVENC_ENCODER
|
|
|
|
case AV_CODEC_ID_AV1:
|
|
|
|
ctx->init_encode_params.encodeGUID = NV_ENC_CODEC_AV1_GUID;
|
|
|
|
break;
|
|
|
|
#endif
|
2016-05-25 16:05:50 +02:00
|
|
|
default:
|
|
|
|
return AVERROR_BUG;
|
|
|
|
}
|
|
|
|
|
2021-04-18 11:17:54 +02:00
|
|
|
nvenc_map_preset(ctx);
|
|
|
|
|
|
|
|
if (ctx->flags & NVENC_DEPRECATED_PRESET)
|
|
|
|
av_log(avctx, AV_LOG_WARNING, "The selected preset is deprecated. Use p1 to p7 + -tune or fast/medium/slow.\n");
|
|
|
|
|
2017-11-11 17:51:58 +02:00
|
|
|
if (avctx->pix_fmt == AV_PIX_FMT_CUDA || avctx->pix_fmt == AV_PIX_FMT_D3D11 || avctx->hw_frames_ctx || avctx->hw_device_ctx) {
|
2016-05-29 14:23:26 +02:00
|
|
|
AVHWFramesContext *frames_ctx;
|
2017-05-07 13:35:25 +02:00
|
|
|
AVHWDeviceContext *hwdev_ctx;
|
2017-11-11 17:51:58 +02:00
|
|
|
AVCUDADeviceContext *cuda_device_hwctx = NULL;
|
|
|
|
#if CONFIG_D3D11VA
|
|
|
|
AVD3D11VADeviceContext *d3d11_device_hwctx = NULL;
|
|
|
|
#endif
|
2016-05-29 14:23:26 +02:00
|
|
|
int ret;
|
2016-05-21 00:08:06 +02:00
|
|
|
|
2017-05-07 13:35:25 +02:00
|
|
|
if (avctx->hw_frames_ctx) {
|
|
|
|
frames_ctx = (AVHWFramesContext*)avctx->hw_frames_ctx->data;
|
2017-11-11 17:51:58 +02:00
|
|
|
if (frames_ctx->format == AV_PIX_FMT_CUDA)
|
|
|
|
cuda_device_hwctx = frames_ctx->device_ctx->hwctx;
|
|
|
|
#if CONFIG_D3D11VA
|
|
|
|
else if (frames_ctx->format == AV_PIX_FMT_D3D11)
|
|
|
|
d3d11_device_hwctx = frames_ctx->device_ctx->hwctx;
|
|
|
|
#endif
|
|
|
|
else
|
|
|
|
return AVERROR(EINVAL);
|
2017-05-07 13:35:25 +02:00
|
|
|
} else if (avctx->hw_device_ctx) {
|
|
|
|
hwdev_ctx = (AVHWDeviceContext*)avctx->hw_device_ctx->data;
|
2017-11-11 17:51:58 +02:00
|
|
|
if (hwdev_ctx->type == AV_HWDEVICE_TYPE_CUDA)
|
|
|
|
cuda_device_hwctx = hwdev_ctx->hwctx;
|
|
|
|
#if CONFIG_D3D11VA
|
|
|
|
else if (hwdev_ctx->type == AV_HWDEVICE_TYPE_D3D11VA)
|
|
|
|
d3d11_device_hwctx = hwdev_ctx->hwctx;
|
|
|
|
#endif
|
|
|
|
else
|
|
|
|
return AVERROR(EINVAL);
|
2017-05-07 13:35:25 +02:00
|
|
|
} else {
|
2016-05-21 00:08:06 +02:00
|
|
|
return AVERROR(EINVAL);
|
2017-05-07 13:35:25 +02:00
|
|
|
}
|
2016-05-21 00:08:06 +02:00
|
|
|
|
2017-11-11 17:51:58 +02:00
|
|
|
if (cuda_device_hwctx) {
|
|
|
|
ctx->cu_context = cuda_device_hwctx->cuda_ctx;
|
2019-09-27 18:30:10 +02:00
|
|
|
ctx->cu_stream = cuda_device_hwctx->stream;
|
2017-11-11 17:51:58 +02:00
|
|
|
}
|
|
|
|
#if CONFIG_D3D11VA
|
|
|
|
else if (d3d11_device_hwctx) {
|
|
|
|
ctx->d3d11_device = d3d11_device_hwctx->device;
|
|
|
|
ID3D11Device_AddRef(ctx->d3d11_device);
|
|
|
|
}
|
|
|
|
#endif
|
2014-11-30 01:04:37 +02:00
|
|
|
|
2016-05-29 14:23:26 +02:00
|
|
|
ret = nvenc_open_session(avctx);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
2014-11-30 01:04:37 +02:00
|
|
|
|
2016-05-29 14:23:26 +02:00
|
|
|
ret = nvenc_check_capabilities(avctx);
|
|
|
|
if (ret < 0) {
|
|
|
|
av_log(avctx, AV_LOG_FATAL, "Provided device doesn't support required NVENC features\n");
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
int i, nb_devices = 0;
|
2014-11-30 01:04:37 +02:00
|
|
|
|
2018-11-11 08:47:28 +02:00
|
|
|
if (CHECK_CU(dl_fn->cuda_dl->cuInit(0)) < 0)
|
2016-05-29 14:23:26 +02:00
|
|
|
return AVERROR_UNKNOWN;
|
2014-11-30 01:04:37 +02:00
|
|
|
|
2018-11-11 08:47:28 +02:00
|
|
|
if (CHECK_CU(dl_fn->cuda_dl->cuDeviceGetCount(&nb_devices)) < 0)
|
2016-05-29 14:23:26 +02:00
|
|
|
return AVERROR_UNKNOWN;
|
2014-11-30 01:04:37 +02:00
|
|
|
|
2016-05-29 14:23:26 +02:00
|
|
|
if (!nb_devices) {
|
|
|
|
av_log(avctx, AV_LOG_FATAL, "No CUDA capable devices found\n");
|
|
|
|
return AVERROR_EXTERNAL;
|
|
|
|
}
|
2016-05-21 00:08:06 +02:00
|
|
|
|
2016-05-29 14:23:26 +02:00
|
|
|
av_log(avctx, AV_LOG_VERBOSE, "%d CUDA capable devices found\n", nb_devices);
|
2016-05-20 16:49:24 +02:00
|
|
|
|
2016-05-29 14:23:26 +02:00
|
|
|
dl_fn->nvenc_device_count = 0;
|
|
|
|
for (i = 0; i < nb_devices; ++i) {
|
|
|
|
if ((nvenc_check_device(avctx, i)) >= 0 && ctx->device != LIST_DEVICES)
|
|
|
|
return 0;
|
|
|
|
}
|
2016-05-20 16:49:24 +02:00
|
|
|
|
2016-05-29 14:23:26 +02:00
|
|
|
if (ctx->device == LIST_DEVICES)
|
|
|
|
return AVERROR_EXIT;
|
2016-05-20 16:49:24 +02:00
|
|
|
|
2016-05-29 14:23:26 +02:00
|
|
|
if (!dl_fn->nvenc_device_count) {
|
2019-10-27 04:30:54 +02:00
|
|
|
av_log(avctx, AV_LOG_FATAL, "No capable devices found\n");
|
2016-05-29 14:23:26 +02:00
|
|
|
return AVERROR_EXTERNAL;
|
|
|
|
}
|
2014-11-30 01:04:37 +02:00
|
|
|
|
2017-01-19 00:01:28 +02:00
|
|
|
av_log(avctx, AV_LOG_FATAL, "Requested GPU %d, but only %d GPUs are available!\n", ctx->device, nb_devices);
|
2016-05-29 14:23:26 +02:00
|
|
|
return AVERROR(EINVAL);
|
2016-05-20 16:49:24 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static av_cold void set_constqp(AVCodecContext *avctx)
|
|
|
|
{
|
|
|
|
NvencContext *ctx = avctx->priv_data;
|
2016-05-25 18:39:54 +02:00
|
|
|
NV_ENC_RC_PARAMS *rc = &ctx->encode_config.rcParams;
|
2022-11-05 22:17:37 +02:00
|
|
|
#if CONFIG_AV1_NVENC_ENCODER
|
|
|
|
int qmax = avctx->codec->id == AV_CODEC_ID_AV1 ? 255 : 51;
|
|
|
|
#else
|
|
|
|
int qmax = 51;
|
|
|
|
#endif
|
2016-05-25 18:39:54 +02:00
|
|
|
|
|
|
|
rc->rateControlMode = NV_ENC_PARAMS_RC_CONSTQP;
|
2017-03-17 06:12:25 +02:00
|
|
|
|
|
|
|
if (ctx->init_qp_p >= 0) {
|
|
|
|
rc->constQP.qpInterP = ctx->init_qp_p;
|
|
|
|
if (ctx->init_qp_i >= 0 && ctx->init_qp_b >= 0) {
|
|
|
|
rc->constQP.qpIntra = ctx->init_qp_i;
|
|
|
|
rc->constQP.qpInterB = ctx->init_qp_b;
|
|
|
|
} else if (avctx->i_quant_factor != 0.0 && avctx->b_quant_factor != 0.0) {
|
|
|
|
rc->constQP.qpIntra = av_clip(
|
2022-11-05 22:17:37 +02:00
|
|
|
rc->constQP.qpInterP * fabs(avctx->i_quant_factor) + avctx->i_quant_offset + 0.5, 0, qmax);
|
2017-03-17 06:12:25 +02:00
|
|
|
rc->constQP.qpInterB = av_clip(
|
2022-11-05 22:17:37 +02:00
|
|
|
rc->constQP.qpInterP * fabs(avctx->b_quant_factor) + avctx->b_quant_offset + 0.5, 0, qmax);
|
2017-03-17 06:12:25 +02:00
|
|
|
} else {
|
|
|
|
rc->constQP.qpIntra = rc->constQP.qpInterP;
|
|
|
|
rc->constQP.qpInterB = rc->constQP.qpInterP;
|
|
|
|
}
|
2017-03-23 18:01:40 +02:00
|
|
|
} else if (ctx->cqp >= 0) {
|
2017-03-23 18:10:25 +02:00
|
|
|
rc->constQP.qpInterP = rc->constQP.qpInterB = rc->constQP.qpIntra = ctx->cqp;
|
|
|
|
if (avctx->b_quant_factor != 0.0)
|
2022-11-05 22:17:37 +02:00
|
|
|
rc->constQP.qpInterB = av_clip(ctx->cqp * fabs(avctx->b_quant_factor) + avctx->b_quant_offset + 0.5, 0, qmax);
|
2017-03-23 18:10:25 +02:00
|
|
|
if (avctx->i_quant_factor != 0.0)
|
2022-11-05 22:17:37 +02:00
|
|
|
rc->constQP.qpIntra = av_clip(ctx->cqp * fabs(avctx->i_quant_factor) + avctx->i_quant_offset + 0.5, 0, qmax);
|
2017-03-17 06:12:25 +02:00
|
|
|
}
|
2016-05-20 16:49:24 +02:00
|
|
|
|
2016-05-25 18:39:54 +02:00
|
|
|
avctx->qmin = -1;
|
|
|
|
avctx->qmax = -1;
|
2016-05-20 16:49:24 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
static av_cold void set_vbr(AVCodecContext *avctx)
|
|
|
|
{
|
|
|
|
NvencContext *ctx = avctx->priv_data;
|
2016-05-25 18:39:54 +02:00
|
|
|
NV_ENC_RC_PARAMS *rc = &ctx->encode_config.rcParams;
|
|
|
|
int qp_inter_p;
|
2022-11-05 22:17:37 +02:00
|
|
|
#if CONFIG_AV1_NVENC_ENCODER
|
|
|
|
int qmax = avctx->codec->id == AV_CODEC_ID_AV1 ? 255 : 51;
|
|
|
|
#else
|
|
|
|
int qmax = 51;
|
|
|
|
#endif
|
2016-05-25 18:39:54 +02:00
|
|
|
|
|
|
|
if (avctx->qmin >= 0 && avctx->qmax >= 0) {
|
|
|
|
rc->enableMinQP = 1;
|
|
|
|
rc->enableMaxQP = 1;
|
|
|
|
|
|
|
|
rc->minQP.qpInterB = avctx->qmin;
|
|
|
|
rc->minQP.qpInterP = avctx->qmin;
|
2017-03-21 00:04:28 +02:00
|
|
|
rc->minQP.qpIntra = avctx->qmin;
|
2016-05-20 16:49:24 +02:00
|
|
|
|
2016-05-25 18:39:54 +02:00
|
|
|
rc->maxQP.qpInterB = avctx->qmax;
|
|
|
|
rc->maxQP.qpInterP = avctx->qmax;
|
|
|
|
rc->maxQP.qpIntra = avctx->qmax;
|
2016-05-20 16:49:24 +02:00
|
|
|
|
2016-05-25 18:39:54 +02:00
|
|
|
qp_inter_p = (avctx->qmax + 3 * avctx->qmin) / 4; // biased towards Qmin
|
2016-05-31 17:00:07 +02:00
|
|
|
} else if (avctx->qmin >= 0) {
|
|
|
|
rc->enableMinQP = 1;
|
|
|
|
|
|
|
|
rc->minQP.qpInterB = avctx->qmin;
|
|
|
|
rc->minQP.qpInterP = avctx->qmin;
|
|
|
|
rc->minQP.qpIntra = avctx->qmin;
|
|
|
|
|
|
|
|
qp_inter_p = avctx->qmin;
|
2016-05-25 18:39:54 +02:00
|
|
|
} else {
|
|
|
|
qp_inter_p = 26; // default to 26
|
|
|
|
}
|
|
|
|
|
|
|
|
rc->enableInitialRCQP = 1;
|
2016-05-20 16:49:24 +02:00
|
|
|
|
2017-02-28 07:39:12 +02:00
|
|
|
if (ctx->init_qp_p < 0) {
|
|
|
|
rc->initialRCQP.qpInterP = qp_inter_p;
|
2016-05-25 18:39:54 +02:00
|
|
|
} else {
|
2017-02-28 07:39:12 +02:00
|
|
|
rc->initialRCQP.qpInterP = ctx->init_qp_p;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (ctx->init_qp_i < 0) {
|
|
|
|
if (avctx->i_quant_factor != 0.0 && avctx->b_quant_factor != 0.0) {
|
|
|
|
rc->initialRCQP.qpIntra = av_clip(
|
2022-11-05 22:17:37 +02:00
|
|
|
rc->initialRCQP.qpInterP * fabs(avctx->i_quant_factor) + avctx->i_quant_offset + 0.5, 0, qmax);
|
2017-02-28 07:39:12 +02:00
|
|
|
} else {
|
|
|
|
rc->initialRCQP.qpIntra = rc->initialRCQP.qpInterP;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
rc->initialRCQP.qpIntra = ctx->init_qp_i;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (ctx->init_qp_b < 0) {
|
|
|
|
if (avctx->i_quant_factor != 0.0 && avctx->b_quant_factor != 0.0) {
|
|
|
|
rc->initialRCQP.qpInterB = av_clip(
|
2022-11-05 22:17:37 +02:00
|
|
|
rc->initialRCQP.qpInterP * fabs(avctx->b_quant_factor) + avctx->b_quant_offset + 0.5, 0, qmax);
|
2017-02-28 07:39:12 +02:00
|
|
|
} else {
|
|
|
|
rc->initialRCQP.qpInterB = rc->initialRCQP.qpInterP;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
rc->initialRCQP.qpInterB = ctx->init_qp_b;
|
2016-05-25 18:39:54 +02:00
|
|
|
}
|
2016-05-20 16:49:24 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
static av_cold void set_lossless(AVCodecContext *avctx)
|
|
|
|
{
|
|
|
|
NvencContext *ctx = avctx->priv_data;
|
2016-05-25 18:39:54 +02:00
|
|
|
NV_ENC_RC_PARAMS *rc = &ctx->encode_config.rcParams;
|
2016-05-20 16:49:24 +02:00
|
|
|
|
2016-05-25 18:39:54 +02:00
|
|
|
rc->rateControlMode = NV_ENC_PARAMS_RC_CONSTQP;
|
|
|
|
rc->constQP.qpInterB = 0;
|
|
|
|
rc->constQP.qpInterP = 0;
|
2017-03-21 00:04:28 +02:00
|
|
|
rc->constQP.qpIntra = 0;
|
2016-05-25 18:39:54 +02:00
|
|
|
|
|
|
|
avctx->qmin = -1;
|
|
|
|
avctx->qmax = -1;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void nvenc_override_rate_control(AVCodecContext *avctx)
|
|
|
|
{
|
|
|
|
NvencContext *ctx = avctx->priv_data;
|
|
|
|
NV_ENC_RC_PARAMS *rc = &ctx->encode_config.rcParams;
|
|
|
|
|
|
|
|
switch (ctx->rc) {
|
|
|
|
case NV_ENC_PARAMS_RC_CONSTQP:
|
|
|
|
set_constqp(avctx);
|
|
|
|
return;
|
2023-06-01 23:46:46 +02:00
|
|
|
#ifndef NVENC_NO_DEPRECATED_RC
|
2016-05-25 18:39:54 +02:00
|
|
|
case NV_ENC_PARAMS_RC_VBR_MINQP:
|
|
|
|
if (avctx->qmin < 0) {
|
|
|
|
av_log(avctx, AV_LOG_WARNING,
|
|
|
|
"The variable bitrate rate-control requires "
|
|
|
|
"the 'qmin' option set.\n");
|
|
|
|
set_vbr(avctx);
|
|
|
|
return;
|
|
|
|
}
|
2017-02-24 03:42:27 +02:00
|
|
|
/* fall through */
|
2017-05-09 13:57:39 +02:00
|
|
|
case NV_ENC_PARAMS_RC_VBR_HQ:
|
2023-06-01 23:46:46 +02:00
|
|
|
#endif
|
2017-02-24 03:42:27 +02:00
|
|
|
case NV_ENC_PARAMS_RC_VBR:
|
2016-05-25 18:39:54 +02:00
|
|
|
set_vbr(avctx);
|
|
|
|
break;
|
|
|
|
case NV_ENC_PARAMS_RC_CBR:
|
2023-06-01 23:46:46 +02:00
|
|
|
#ifndef NVENC_NO_DEPRECATED_RC
|
2017-05-09 13:57:39 +02:00
|
|
|
case NV_ENC_PARAMS_RC_CBR_HQ:
|
|
|
|
case NV_ENC_PARAMS_RC_CBR_LOWDELAY_HQ:
|
2023-06-01 23:46:46 +02:00
|
|
|
#endif
|
2016-05-31 16:55:24 +02:00
|
|
|
break;
|
2016-05-25 18:39:54 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
rc->rateControlMode = ctx->rc;
|
2016-05-20 16:49:24 +02:00
|
|
|
}
|
|
|
|
|
avcodec/nvenc: better surface allocation alghoritm, fix rc_lookahead
User selectable surfaces are not working correctly, if you set number of
surfaces on cmdline, it will always use minimum 32 or 48 depends on
selected resolution, but in nvenc it is not necessary to use so many
surfaces.
So from now you can define as low as 1 surface and nvenc will still
work, it will ofcourse lower GPU memory usage by 95% and async_delay to zero
That was the easy part, now littlebit more...
Next part of this patch is to always prefer rc_lookahead to be more
important for number of surfaces, than user defined surfaces value.
Maximum rc_lookahead from nvidia documentation is 32, but could increase
in future generations so there is no limit for this yet. Value
async_depth is still accepted and prefered over rc_lookahead.
There were also bug when you request more than rc_lookahead > 31, it
will always set maximum 31, because surface numbers recalculation was
after setting lookahead, which is now fixed.
Results:
If you set -rc_lookahead 32 and -bf 3 it will now use only 40 surfaces
and lower GPU memory usage by 20%, also it will now increase PSNR by 0.012dB
Two more comments:
1. from my internal test, i don't understand addition of 4 more surfaces
when lookahead is calculated, i didn't used this and everything works as
with those 4 more extra surfaces, does anybody know what is going on
there? I looks like it was used for B frames which are calculated
separately, because B frames maximum is 4.
2. rc_lookahead is defined default to -1, but in test condition if
(ctx->rc_lookahead) which sets lookahead it will be always true, i don't
know if this is intended behavior, so in default behavior is lookahead
always on!
This is default condition when rc_lokkahead is -1 (not defined on
cmdline), whis is maybe something that is not intended:
ctx->encode_config.rcParams.enableLookahead = 1;
ctx->encode_config.rcParams.lookaheadDepth = 0;
ctx->encode_config.rcParams.disableIadapt = 0;
ctx->encode_config.rcParams.disableBadapt = 0;
Signed-off-by: Timo Rothenpieler <timo@rothenpieler.org>
2016-11-21 13:17:43 +02:00
|
|
|
static av_cold int nvenc_recalc_surfaces(AVCodecContext *avctx)
|
|
|
|
{
|
|
|
|
NvencContext *ctx = avctx->priv_data;
|
2017-04-25 23:57:56 +02:00
|
|
|
// default minimum of 4 surfaces
|
|
|
|
// multiply by 2 for number of NVENCs on gpu (hardcode to 2)
|
|
|
|
// another multiply by 2 to avoid blocking next PBB group
|
|
|
|
int nb_surfaces = FFMAX(4, ctx->encode_config.frameIntervalP * 2 * 2);
|
avcodec/nvenc: better surface allocation alghoritm, fix rc_lookahead
User selectable surfaces are not working correctly, if you set number of
surfaces on cmdline, it will always use minimum 32 or 48 depends on
selected resolution, but in nvenc it is not necessary to use so many
surfaces.
So from now you can define as low as 1 surface and nvenc will still
work, it will ofcourse lower GPU memory usage by 95% and async_delay to zero
That was the easy part, now littlebit more...
Next part of this patch is to always prefer rc_lookahead to be more
important for number of surfaces, than user defined surfaces value.
Maximum rc_lookahead from nvidia documentation is 32, but could increase
in future generations so there is no limit for this yet. Value
async_depth is still accepted and prefered over rc_lookahead.
There were also bug when you request more than rc_lookahead > 31, it
will always set maximum 31, because surface numbers recalculation was
after setting lookahead, which is now fixed.
Results:
If you set -rc_lookahead 32 and -bf 3 it will now use only 40 surfaces
and lower GPU memory usage by 20%, also it will now increase PSNR by 0.012dB
Two more comments:
1. from my internal test, i don't understand addition of 4 more surfaces
when lookahead is calculated, i didn't used this and everything works as
with those 4 more extra surfaces, does anybody know what is going on
there? I looks like it was used for B frames which are calculated
separately, because B frames maximum is 4.
2. rc_lookahead is defined default to -1, but in test condition if
(ctx->rc_lookahead) which sets lookahead it will be always true, i don't
know if this is intended behavior, so in default behavior is lookahead
always on!
This is default condition when rc_lokkahead is -1 (not defined on
cmdline), whis is maybe something that is not intended:
ctx->encode_config.rcParams.enableLookahead = 1;
ctx->encode_config.rcParams.lookaheadDepth = 0;
ctx->encode_config.rcParams.disableIadapt = 0;
ctx->encode_config.rcParams.disableBadapt = 0;
Signed-off-by: Timo Rothenpieler <timo@rothenpieler.org>
2016-11-21 13:17:43 +02:00
|
|
|
|
2017-04-25 23:57:56 +02:00
|
|
|
// lookahead enabled
|
avcodec/nvenc: better surface allocation alghoritm, fix rc_lookahead
User selectable surfaces are not working correctly, if you set number of
surfaces on cmdline, it will always use minimum 32 or 48 depends on
selected resolution, but in nvenc it is not necessary to use so many
surfaces.
So from now you can define as low as 1 surface and nvenc will still
work, it will ofcourse lower GPU memory usage by 95% and async_delay to zero
That was the easy part, now littlebit more...
Next part of this patch is to always prefer rc_lookahead to be more
important for number of surfaces, than user defined surfaces value.
Maximum rc_lookahead from nvidia documentation is 32, but could increase
in future generations so there is no limit for this yet. Value
async_depth is still accepted and prefered over rc_lookahead.
There were also bug when you request more than rc_lookahead > 31, it
will always set maximum 31, because surface numbers recalculation was
after setting lookahead, which is now fixed.
Results:
If you set -rc_lookahead 32 and -bf 3 it will now use only 40 surfaces
and lower GPU memory usage by 20%, also it will now increase PSNR by 0.012dB
Two more comments:
1. from my internal test, i don't understand addition of 4 more surfaces
when lookahead is calculated, i didn't used this and everything works as
with those 4 more extra surfaces, does anybody know what is going on
there? I looks like it was used for B frames which are calculated
separately, because B frames maximum is 4.
2. rc_lookahead is defined default to -1, but in test condition if
(ctx->rc_lookahead) which sets lookahead it will be always true, i don't
know if this is intended behavior, so in default behavior is lookahead
always on!
This is default condition when rc_lokkahead is -1 (not defined on
cmdline), whis is maybe something that is not intended:
ctx->encode_config.rcParams.enableLookahead = 1;
ctx->encode_config.rcParams.lookaheadDepth = 0;
ctx->encode_config.rcParams.disableIadapt = 0;
ctx->encode_config.rcParams.disableBadapt = 0;
Signed-off-by: Timo Rothenpieler <timo@rothenpieler.org>
2016-11-21 13:17:43 +02:00
|
|
|
if (ctx->rc_lookahead > 0) {
|
2017-04-25 23:57:56 +02:00
|
|
|
// +1 is to account for lkd_bound calculation later
|
|
|
|
// +4 is to allow sufficient pipelining with lookahead
|
|
|
|
nb_surfaces = FFMAX(1, FFMAX(nb_surfaces, ctx->rc_lookahead + ctx->encode_config.frameIntervalP + 1 + 4));
|
|
|
|
if (nb_surfaces > ctx->nb_surfaces && ctx->nb_surfaces > 0)
|
|
|
|
{
|
avcodec/nvenc: better surface allocation alghoritm, fix rc_lookahead
User selectable surfaces are not working correctly, if you set number of
surfaces on cmdline, it will always use minimum 32 or 48 depends on
selected resolution, but in nvenc it is not necessary to use so many
surfaces.
So from now you can define as low as 1 surface and nvenc will still
work, it will ofcourse lower GPU memory usage by 95% and async_delay to zero
That was the easy part, now littlebit more...
Next part of this patch is to always prefer rc_lookahead to be more
important for number of surfaces, than user defined surfaces value.
Maximum rc_lookahead from nvidia documentation is 32, but could increase
in future generations so there is no limit for this yet. Value
async_depth is still accepted and prefered over rc_lookahead.
There were also bug when you request more than rc_lookahead > 31, it
will always set maximum 31, because surface numbers recalculation was
after setting lookahead, which is now fixed.
Results:
If you set -rc_lookahead 32 and -bf 3 it will now use only 40 surfaces
and lower GPU memory usage by 20%, also it will now increase PSNR by 0.012dB
Two more comments:
1. from my internal test, i don't understand addition of 4 more surfaces
when lookahead is calculated, i didn't used this and everything works as
with those 4 more extra surfaces, does anybody know what is going on
there? I looks like it was used for B frames which are calculated
separately, because B frames maximum is 4.
2. rc_lookahead is defined default to -1, but in test condition if
(ctx->rc_lookahead) which sets lookahead it will be always true, i don't
know if this is intended behavior, so in default behavior is lookahead
always on!
This is default condition when rc_lokkahead is -1 (not defined on
cmdline), whis is maybe something that is not intended:
ctx->encode_config.rcParams.enableLookahead = 1;
ctx->encode_config.rcParams.lookaheadDepth = 0;
ctx->encode_config.rcParams.disableIadapt = 0;
ctx->encode_config.rcParams.disableBadapt = 0;
Signed-off-by: Timo Rothenpieler <timo@rothenpieler.org>
2016-11-21 13:17:43 +02:00
|
|
|
av_log(avctx, AV_LOG_WARNING,
|
|
|
|
"Defined rc_lookahead requires more surfaces, "
|
|
|
|
"increasing used surfaces %d -> %d\n", ctx->nb_surfaces, nb_surfaces);
|
|
|
|
}
|
2017-04-25 23:57:56 +02:00
|
|
|
ctx->nb_surfaces = FFMAX(nb_surfaces, ctx->nb_surfaces);
|
|
|
|
} else {
|
|
|
|
if (ctx->encode_config.frameIntervalP > 1 && ctx->nb_surfaces < nb_surfaces && ctx->nb_surfaces > 0)
|
|
|
|
{
|
|
|
|
av_log(avctx, AV_LOG_WARNING,
|
|
|
|
"Defined b-frame requires more surfaces, "
|
|
|
|
"increasing used surfaces %d -> %d\n", ctx->nb_surfaces, nb_surfaces);
|
|
|
|
ctx->nb_surfaces = FFMAX(ctx->nb_surfaces, nb_surfaces);
|
|
|
|
}
|
|
|
|
else if (ctx->nb_surfaces <= 0)
|
|
|
|
ctx->nb_surfaces = nb_surfaces;
|
|
|
|
// otherwise use user specified value
|
avcodec/nvenc: better surface allocation alghoritm, fix rc_lookahead
User selectable surfaces are not working correctly, if you set number of
surfaces on cmdline, it will always use minimum 32 or 48 depends on
selected resolution, but in nvenc it is not necessary to use so many
surfaces.
So from now you can define as low as 1 surface and nvenc will still
work, it will ofcourse lower GPU memory usage by 95% and async_delay to zero
That was the easy part, now littlebit more...
Next part of this patch is to always prefer rc_lookahead to be more
important for number of surfaces, than user defined surfaces value.
Maximum rc_lookahead from nvidia documentation is 32, but could increase
in future generations so there is no limit for this yet. Value
async_depth is still accepted and prefered over rc_lookahead.
There were also bug when you request more than rc_lookahead > 31, it
will always set maximum 31, because surface numbers recalculation was
after setting lookahead, which is now fixed.
Results:
If you set -rc_lookahead 32 and -bf 3 it will now use only 40 surfaces
and lower GPU memory usage by 20%, also it will now increase PSNR by 0.012dB
Two more comments:
1. from my internal test, i don't understand addition of 4 more surfaces
when lookahead is calculated, i didn't used this and everything works as
with those 4 more extra surfaces, does anybody know what is going on
there? I looks like it was used for B frames which are calculated
separately, because B frames maximum is 4.
2. rc_lookahead is defined default to -1, but in test condition if
(ctx->rc_lookahead) which sets lookahead it will be always true, i don't
know if this is intended behavior, so in default behavior is lookahead
always on!
This is default condition when rc_lokkahead is -1 (not defined on
cmdline), whis is maybe something that is not intended:
ctx->encode_config.rcParams.enableLookahead = 1;
ctx->encode_config.rcParams.lookaheadDepth = 0;
ctx->encode_config.rcParams.disableIadapt = 0;
ctx->encode_config.rcParams.disableBadapt = 0;
Signed-off-by: Timo Rothenpieler <timo@rothenpieler.org>
2016-11-21 13:17:43 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
ctx->nb_surfaces = FFMAX(1, FFMIN(MAX_REGISTERED_FRAMES, ctx->nb_surfaces));
|
|
|
|
ctx->async_depth = FFMIN(ctx->async_depth, ctx->nb_surfaces - 1);
|
|
|
|
|
2023-06-16 21:35:45 +02:00
|
|
|
// Output in the worst case will only start when the surface buffer is completely full.
|
|
|
|
// Hence we need to keep at least the max amount of surfaces plus the max reorder delay around.
|
|
|
|
ctx->frame_data_array_nb = ctx->nb_surfaces + ctx->encode_config.frameIntervalP - 1;
|
|
|
|
|
avcodec/nvenc: better surface allocation alghoritm, fix rc_lookahead
User selectable surfaces are not working correctly, if you set number of
surfaces on cmdline, it will always use minimum 32 or 48 depends on
selected resolution, but in nvenc it is not necessary to use so many
surfaces.
So from now you can define as low as 1 surface and nvenc will still
work, it will ofcourse lower GPU memory usage by 95% and async_delay to zero
That was the easy part, now littlebit more...
Next part of this patch is to always prefer rc_lookahead to be more
important for number of surfaces, than user defined surfaces value.
Maximum rc_lookahead from nvidia documentation is 32, but could increase
in future generations so there is no limit for this yet. Value
async_depth is still accepted and prefered over rc_lookahead.
There were also bug when you request more than rc_lookahead > 31, it
will always set maximum 31, because surface numbers recalculation was
after setting lookahead, which is now fixed.
Results:
If you set -rc_lookahead 32 and -bf 3 it will now use only 40 surfaces
and lower GPU memory usage by 20%, also it will now increase PSNR by 0.012dB
Two more comments:
1. from my internal test, i don't understand addition of 4 more surfaces
when lookahead is calculated, i didn't used this and everything works as
with those 4 more extra surfaces, does anybody know what is going on
there? I looks like it was used for B frames which are calculated
separately, because B frames maximum is 4.
2. rc_lookahead is defined default to -1, but in test condition if
(ctx->rc_lookahead) which sets lookahead it will be always true, i don't
know if this is intended behavior, so in default behavior is lookahead
always on!
This is default condition when rc_lokkahead is -1 (not defined on
cmdline), whis is maybe something that is not intended:
ctx->encode_config.rcParams.enableLookahead = 1;
ctx->encode_config.rcParams.lookaheadDepth = 0;
ctx->encode_config.rcParams.disableIadapt = 0;
ctx->encode_config.rcParams.disableBadapt = 0;
Signed-off-by: Timo Rothenpieler <timo@rothenpieler.org>
2016-11-21 13:17:43 +02:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2024-03-31 20:52:27 +02:00
|
|
|
static av_cold int nvenc_setup_rate_control(AVCodecContext *avctx)
|
2016-05-20 16:49:24 +02:00
|
|
|
{
|
|
|
|
NvencContext *ctx = avctx->priv_data;
|
|
|
|
|
2017-03-23 18:01:40 +02:00
|
|
|
if (avctx->global_quality > 0)
|
|
|
|
av_log(avctx, AV_LOG_WARNING, "Using global_quality with nvenc is deprecated. Use qp instead.\n");
|
|
|
|
|
|
|
|
if (ctx->cqp < 0 && avctx->global_quality > 0)
|
|
|
|
ctx->cqp = avctx->global_quality;
|
|
|
|
|
2016-05-20 16:49:24 +02:00
|
|
|
if (avctx->bit_rate > 0) {
|
|
|
|
ctx->encode_config.rcParams.averageBitRate = avctx->bit_rate;
|
|
|
|
} else if (ctx->encode_config.rcParams.averageBitRate > 0) {
|
|
|
|
ctx->encode_config.rcParams.maxBitRate = ctx->encode_config.rcParams.averageBitRate;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (avctx->rc_max_rate > 0)
|
|
|
|
ctx->encode_config.rcParams.maxBitRate = avctx->rc_max_rate;
|
|
|
|
|
2020-03-19 10:35:29 +02:00
|
|
|
#ifdef NVENC_HAVE_MULTIPASS
|
|
|
|
ctx->encode_config.rcParams.multiPass = ctx->multipass;
|
|
|
|
|
2020-10-21 18:45:52 +02:00
|
|
|
if (ctx->flags & NVENC_ONE_PASS)
|
|
|
|
ctx->encode_config.rcParams.multiPass = NV_ENC_MULTI_PASS_DISABLED;
|
2020-10-30 18:26:32 +02:00
|
|
|
if (ctx->flags & NVENC_TWO_PASSES || ctx->twopass > 0)
|
2020-10-21 18:45:52 +02:00
|
|
|
ctx->encode_config.rcParams.multiPass = NV_ENC_TWO_PASS_FULL_RESOLUTION;
|
|
|
|
|
|
|
|
if (ctx->rc < 0) {
|
|
|
|
if (ctx->cbr) {
|
|
|
|
ctx->rc = NV_ENC_PARAMS_RC_CBR;
|
|
|
|
} else if (ctx->cqp >= 0) {
|
|
|
|
ctx->rc = NV_ENC_PARAMS_RC_CONSTQP;
|
2020-10-30 18:21:13 +02:00
|
|
|
} else if (ctx->quality >= 0.0f) {
|
2020-10-21 18:45:52 +02:00
|
|
|
ctx->rc = NV_ENC_PARAMS_RC_VBR;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
#else
|
2016-05-25 18:39:54 +02:00
|
|
|
if (ctx->rc < 0) {
|
|
|
|
if (ctx->flags & NVENC_ONE_PASS)
|
|
|
|
ctx->twopass = 0;
|
|
|
|
if (ctx->flags & NVENC_TWO_PASSES)
|
|
|
|
ctx->twopass = 1;
|
2016-05-20 16:49:24 +02:00
|
|
|
|
2016-05-25 18:39:54 +02:00
|
|
|
if (ctx->twopass < 0)
|
|
|
|
ctx->twopass = (ctx->flags & NVENC_LOWLATENCY) != 0;
|
2016-05-20 16:49:24 +02:00
|
|
|
|
2016-05-25 18:39:54 +02:00
|
|
|
if (ctx->cbr) {
|
2016-05-20 16:49:24 +02:00
|
|
|
if (ctx->twopass) {
|
2017-05-09 13:57:39 +02:00
|
|
|
ctx->rc = NV_ENC_PARAMS_RC_CBR_LOWDELAY_HQ;
|
2016-05-20 16:49:24 +02:00
|
|
|
} else {
|
2016-05-25 18:39:54 +02:00
|
|
|
ctx->rc = NV_ENC_PARAMS_RC_CBR;
|
2016-05-20 16:49:24 +02:00
|
|
|
}
|
2017-03-23 18:01:40 +02:00
|
|
|
} else if (ctx->cqp >= 0) {
|
2016-05-25 18:39:54 +02:00
|
|
|
ctx->rc = NV_ENC_PARAMS_RC_CONSTQP;
|
|
|
|
} else if (ctx->twopass) {
|
2017-05-09 13:57:39 +02:00
|
|
|
ctx->rc = NV_ENC_PARAMS_RC_VBR_HQ;
|
2016-05-25 18:39:54 +02:00
|
|
|
} else if (avctx->qmin >= 0 && avctx->qmax >= 0) {
|
|
|
|
ctx->rc = NV_ENC_PARAMS_RC_VBR_MINQP;
|
2016-05-20 16:49:24 +02:00
|
|
|
}
|
2016-05-25 18:39:54 +02:00
|
|
|
}
|
2020-10-21 18:45:52 +02:00
|
|
|
#endif
|
2016-05-20 16:49:24 +02:00
|
|
|
|
2017-05-09 13:57:39 +02:00
|
|
|
if (ctx->rc >= 0 && ctx->rc & RC_MODE_DEPRECATED) {
|
|
|
|
av_log(avctx, AV_LOG_WARNING, "Specified rc mode is deprecated.\n");
|
2020-10-21 18:17:08 +02:00
|
|
|
av_log(avctx, AV_LOG_WARNING, "Use -rc constqp/cbr/vbr, -tune and -multipass instead.\n");
|
2017-05-09 13:57:39 +02:00
|
|
|
|
|
|
|
ctx->rc &= ~RC_MODE_DEPRECATED;
|
|
|
|
}
|
|
|
|
|
2021-08-09 15:16:58 +02:00
|
|
|
#ifdef NVENC_HAVE_QP_CHROMA_OFFSETS
|
|
|
|
ctx->encode_config.rcParams.cbQPIndexOffset = ctx->qp_cb_offset;
|
|
|
|
ctx->encode_config.rcParams.crQPIndexOffset = ctx->qp_cr_offset;
|
|
|
|
#else
|
|
|
|
if (ctx->qp_cb_offset || ctx->qp_cr_offset)
|
|
|
|
av_log(avctx, AV_LOG_WARNING, "Failed setting QP CB/CR offsets, SDK 11.1 or greater required at compile time.\n");
|
|
|
|
#endif
|
|
|
|
|
2020-03-19 10:35:29 +02:00
|
|
|
#ifdef NVENC_HAVE_LDKFS
|
|
|
|
if (ctx->ldkfs)
|
|
|
|
ctx->encode_config.rcParams.lowDelayKeyFrameScale = ctx->ldkfs;
|
|
|
|
#endif
|
|
|
|
|
2016-05-25 18:39:54 +02:00
|
|
|
if (ctx->flags & NVENC_LOSSLESS) {
|
|
|
|
set_lossless(avctx);
|
2016-05-31 16:53:38 +02:00
|
|
|
} else if (ctx->rc >= 0) {
|
2016-05-25 18:39:54 +02:00
|
|
|
nvenc_override_rate_control(avctx);
|
|
|
|
} else {
|
|
|
|
ctx->encode_config.rcParams.rateControlMode = NV_ENC_PARAMS_RC_VBR;
|
|
|
|
set_vbr(avctx);
|
2016-05-20 16:49:24 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
if (avctx->rc_buffer_size > 0) {
|
|
|
|
ctx->encode_config.rcParams.vbvBufferSize = avctx->rc_buffer_size;
|
|
|
|
} else if (ctx->encode_config.rcParams.averageBitRate > 0) {
|
2018-05-03 02:15:52 +02:00
|
|
|
avctx->rc_buffer_size = ctx->encode_config.rcParams.vbvBufferSize = 2 * ctx->encode_config.rcParams.averageBitRate;
|
2016-05-20 16:49:24 +02:00
|
|
|
}
|
2016-08-25 17:20:03 +02:00
|
|
|
|
2016-09-24 17:55:00 +02:00
|
|
|
if (ctx->aq) {
|
|
|
|
ctx->encode_config.rcParams.enableAQ = 1;
|
|
|
|
ctx->encode_config.rcParams.aqStrength = ctx->aq_strength;
|
|
|
|
av_log(avctx, AV_LOG_VERBOSE, "AQ enabled.\n");
|
2016-08-25 17:20:03 +02:00
|
|
|
}
|
2016-09-24 17:55:00 +02:00
|
|
|
|
|
|
|
if (ctx->temporal_aq) {
|
|
|
|
ctx->encode_config.rcParams.enableTemporalAQ = 1;
|
|
|
|
av_log(avctx, AV_LOG_VERBOSE, "Temporal AQ enabled.\n");
|
|
|
|
}
|
|
|
|
|
2016-12-26 09:49:16 +02:00
|
|
|
if (ctx->rc_lookahead > 0) {
|
2016-09-24 17:55:00 +02:00
|
|
|
int lkd_bound = FFMIN(ctx->nb_surfaces, ctx->async_depth) -
|
|
|
|
ctx->encode_config.frameIntervalP - 4;
|
|
|
|
|
|
|
|
if (lkd_bound < 0) {
|
2022-12-05 22:10:36 +02:00
|
|
|
ctx->encode_config.rcParams.enableLookahead = 0;
|
2016-09-24 17:55:00 +02:00
|
|
|
av_log(avctx, AV_LOG_WARNING,
|
|
|
|
"Lookahead not enabled. Increase buffer delay (-delay).\n");
|
|
|
|
} else {
|
|
|
|
ctx->encode_config.rcParams.enableLookahead = 1;
|
|
|
|
ctx->encode_config.rcParams.lookaheadDepth = av_clip(ctx->rc_lookahead, 0, lkd_bound);
|
|
|
|
ctx->encode_config.rcParams.disableIadapt = ctx->no_scenecut;
|
|
|
|
ctx->encode_config.rcParams.disableBadapt = !ctx->b_adapt;
|
|
|
|
av_log(avctx, AV_LOG_VERBOSE,
|
|
|
|
"Lookahead enabled: depth %d, scenecut %s, B-adapt %s.\n",
|
|
|
|
ctx->encode_config.rcParams.lookaheadDepth,
|
|
|
|
ctx->encode_config.rcParams.disableIadapt ? "disabled" : "enabled",
|
|
|
|
ctx->encode_config.rcParams.disableBadapt ? "disabled" : "enabled");
|
2022-12-05 22:18:42 +02:00
|
|
|
if (ctx->encode_config.rcParams.lookaheadDepth < ctx->rc_lookahead)
|
|
|
|
av_log(avctx, AV_LOG_WARNING, "Clipping lookahead depth to %d (from %d) due to lack of surfaces/delay",
|
|
|
|
ctx->encode_config.rcParams.lookaheadDepth, ctx->rc_lookahead);
|
2024-03-31 20:52:27 +02:00
|
|
|
|
|
|
|
#ifdef NVENC_HAVE_LOOKAHEAD_LEVEL
|
|
|
|
if (ctx->lookahead_level >= 0) {
|
|
|
|
switch (ctx->lookahead_level) {
|
|
|
|
case NV_ENC_LOOKAHEAD_LEVEL_0:
|
|
|
|
case NV_ENC_LOOKAHEAD_LEVEL_1:
|
|
|
|
case NV_ENC_LOOKAHEAD_LEVEL_2:
|
|
|
|
case NV_ENC_LOOKAHEAD_LEVEL_3:
|
|
|
|
case NV_ENC_LOOKAHEAD_LEVEL_AUTOSELECT:
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
av_log(avctx, AV_LOG_ERROR, "Invalid lookahead level.\n");
|
|
|
|
return AVERROR(EINVAL);
|
|
|
|
}
|
|
|
|
|
|
|
|
ctx->encode_config.rcParams.lookaheadLevel = ctx->lookahead_level;
|
|
|
|
}
|
|
|
|
#endif
|
2016-09-24 17:55:00 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (ctx->strict_gop) {
|
|
|
|
ctx->encode_config.rcParams.strictGOPTarget = 1;
|
|
|
|
av_log(avctx, AV_LOG_VERBOSE, "Strict GOP target enabled.\n");
|
|
|
|
}
|
|
|
|
|
|
|
|
if (ctx->nonref_p)
|
|
|
|
ctx->encode_config.rcParams.enableNonRefP = 1;
|
|
|
|
|
|
|
|
if (ctx->zerolatency)
|
|
|
|
ctx->encode_config.rcParams.zeroReorderDelay = 1;
|
|
|
|
|
2020-04-20 12:53:36 +02:00
|
|
|
if (ctx->quality) {
|
2017-05-10 08:41:17 +02:00
|
|
|
//convert from float to fixed point 8.8
|
|
|
|
int tmp_quality = (int)(ctx->quality * 256.0f);
|
|
|
|
ctx->encode_config.rcParams.targetQuality = (uint8_t)(tmp_quality >> 8);
|
|
|
|
ctx->encode_config.rcParams.targetQualityLSB = (uint8_t)(tmp_quality & 0xff);
|
2020-04-20 12:53:36 +02:00
|
|
|
|
|
|
|
av_log(avctx, AV_LOG_VERBOSE, "CQ(%d) mode enabled.\n", tmp_quality);
|
|
|
|
|
2022-12-08 13:31:00 +02:00
|
|
|
// CQ mode shall discard avg bitrate/vbv buffer size and honor only max bitrate
|
2020-06-03 15:12:12 +02:00
|
|
|
ctx->encode_config.rcParams.averageBitRate = avctx->bit_rate = 0;
|
2022-12-08 13:31:00 +02:00
|
|
|
ctx->encode_config.rcParams.vbvBufferSize = avctx->rc_buffer_size = 0;
|
2020-06-03 15:12:12 +02:00
|
|
|
ctx->encode_config.rcParams.maxBitRate = avctx->rc_max_rate;
|
2017-05-10 08:41:17 +02:00
|
|
|
}
|
2024-03-31 20:52:27 +02:00
|
|
|
|
|
|
|
return 0;
|
2016-05-20 16:49:24 +02:00
|
|
|
}
|
|
|
|
|
2016-05-25 16:05:50 +02:00
|
|
|
static av_cold int nvenc_setup_h264_config(AVCodecContext *avctx)
|
2016-05-20 16:49:24 +02:00
|
|
|
{
|
2016-05-25 16:05:50 +02:00
|
|
|
NvencContext *ctx = avctx->priv_data;
|
|
|
|
NV_ENC_CONFIG *cc = &ctx->encode_config;
|
|
|
|
NV_ENC_CONFIG_H264 *h264 = &cc->encodeCodecConfig.h264Config;
|
|
|
|
NV_ENC_CONFIG_H264_VUI_PARAMETERS *vui = &h264->h264VUIParameters;
|
2016-05-20 16:49:24 +02:00
|
|
|
|
2022-08-06 20:58:48 +02:00
|
|
|
const AVPixFmtDescriptor *pixdesc = av_pix_fmt_desc_get(ctx->data_pix_fmt);
|
|
|
|
|
|
|
|
if ((pixdesc->flags & AV_PIX_FMT_FLAG_RGB) && !IS_GBRP(ctx->data_pix_fmt)) {
|
|
|
|
vui->colourMatrix = AVCOL_SPC_BT470BG;
|
|
|
|
vui->colourPrimaries = avctx->color_primaries;
|
|
|
|
vui->transferCharacteristics = avctx->color_trc;
|
|
|
|
vui->videoFullRangeFlag = 0;
|
|
|
|
} else {
|
|
|
|
vui->colourMatrix = IS_GBRP(ctx->data_pix_fmt) ? AVCOL_SPC_RGB : avctx->colorspace;
|
|
|
|
vui->colourPrimaries = avctx->color_primaries;
|
|
|
|
vui->transferCharacteristics = avctx->color_trc;
|
|
|
|
vui->videoFullRangeFlag = (avctx->color_range == AVCOL_RANGE_JPEG
|
|
|
|
|| ctx->data_pix_fmt == AV_PIX_FMT_YUVJ420P || ctx->data_pix_fmt == AV_PIX_FMT_YUVJ422P || ctx->data_pix_fmt == AV_PIX_FMT_YUVJ444P);
|
|
|
|
}
|
2016-05-20 16:49:24 +02:00
|
|
|
|
2016-05-25 16:05:50 +02:00
|
|
|
vui->colourDescriptionPresentFlag =
|
2021-03-30 22:08:49 +02:00
|
|
|
(vui->colourMatrix != 2 || vui->colourPrimaries != 2 || vui->transferCharacteristics != 2);
|
2016-05-20 16:49:24 +02:00
|
|
|
|
2016-05-25 16:05:50 +02:00
|
|
|
vui->videoSignalTypePresentFlag =
|
|
|
|
(vui->colourDescriptionPresentFlag
|
|
|
|
|| vui->videoFormat != 5
|
|
|
|
|| vui->videoFullRangeFlag != 0);
|
2016-05-20 16:49:24 +02:00
|
|
|
|
2023-07-27 04:26:23 +02:00
|
|
|
if (ctx->max_slice_size > 0) {
|
|
|
|
h264->sliceMode = 1;
|
|
|
|
h264->sliceModeData = ctx->max_slice_size;
|
|
|
|
} else {
|
|
|
|
h264->sliceMode = 3;
|
|
|
|
h264->sliceModeData = avctx->slices > 0 ? avctx->slices : 1;
|
|
|
|
}
|
2016-05-20 16:49:24 +02:00
|
|
|
|
2021-09-06 04:01:58 +02:00
|
|
|
if (ctx->intra_refresh) {
|
|
|
|
h264->enableIntraRefresh = 1;
|
2023-06-22 12:18:19 +02:00
|
|
|
h264->intraRefreshPeriod = cc->gopLength;
|
|
|
|
h264->intraRefreshCnt = cc->gopLength - 1;
|
2023-07-06 14:00:48 +02:00
|
|
|
cc->gopLength = NVENC_INFINITE_GOPLENGTH;
|
2021-09-02 12:38:57 +02:00
|
|
|
#ifdef NVENC_HAVE_SINGLE_SLICE_INTRA_REFRESH
|
|
|
|
h264->singleSliceIntraRefresh = ctx->single_slice_intra_refresh;
|
|
|
|
#endif
|
2021-09-06 04:01:58 +02:00
|
|
|
}
|
|
|
|
|
2021-09-02 12:38:58 +02:00
|
|
|
if (ctx->constrained_encoding)
|
|
|
|
h264->enableConstrainedEncoding = 1;
|
|
|
|
|
2016-05-25 16:05:50 +02:00
|
|
|
h264->disableSPSPPS = (avctx->flags & AV_CODEC_FLAG_GLOBAL_HEADER) ? 1 : 0;
|
2016-05-25 18:39:54 +02:00
|
|
|
h264->repeatSPSPPS = (avctx->flags & AV_CODEC_FLAG_GLOBAL_HEADER) ? 0 : 1;
|
2016-12-30 23:02:42 +02:00
|
|
|
h264->outputAUD = ctx->aud;
|
2016-05-20 16:49:24 +02:00
|
|
|
|
2019-09-27 17:55:23 +02:00
|
|
|
if (ctx->dpb_size >= 0) {
|
2016-05-25 18:39:54 +02:00
|
|
|
/* 0 means "let the hardware decide" */
|
2019-09-27 17:55:23 +02:00
|
|
|
h264->maxNumRefFrames = ctx->dpb_size;
|
2016-05-25 18:39:54 +02:00
|
|
|
}
|
2021-09-06 04:01:58 +02:00
|
|
|
|
2023-07-06 21:57:38 +02:00
|
|
|
h264->idrPeriod = cc->gopLength;
|
2016-05-25 18:39:54 +02:00
|
|
|
|
|
|
|
if (IS_CBR(cc->rcParams.rateControlMode)) {
|
|
|
|
h264->outputBufferingPeriodSEI = 1;
|
|
|
|
}
|
|
|
|
|
2017-09-02 15:39:24 +02:00
|
|
|
h264->outputPictureTimingSEI = 1;
|
|
|
|
|
2023-06-01 23:46:46 +02:00
|
|
|
#ifndef NVENC_NO_DEPRECATED_RC
|
2017-05-09 13:57:39 +02:00
|
|
|
if (cc->rcParams.rateControlMode == NV_ENC_PARAMS_RC_CBR_LOWDELAY_HQ ||
|
|
|
|
cc->rcParams.rateControlMode == NV_ENC_PARAMS_RC_CBR_HQ ||
|
|
|
|
cc->rcParams.rateControlMode == NV_ENC_PARAMS_RC_VBR_HQ) {
|
2016-05-25 18:39:54 +02:00
|
|
|
h264->adaptiveTransformMode = NV_ENC_H264_ADAPTIVE_TRANSFORM_ENABLE;
|
|
|
|
h264->fmoMode = NV_ENC_H264_FMO_DISABLE;
|
|
|
|
}
|
2023-06-01 23:46:46 +02:00
|
|
|
#endif
|
2016-05-20 16:49:24 +02:00
|
|
|
|
2016-05-25 16:26:25 +02:00
|
|
|
if (ctx->flags & NVENC_LOSSLESS) {
|
|
|
|
h264->qpPrimeYZeroTransformBypassFlag = 1;
|
|
|
|
} else {
|
|
|
|
switch(ctx->profile) {
|
|
|
|
case NV_ENC_H264_PROFILE_BASELINE:
|
2016-05-25 16:05:50 +02:00
|
|
|
cc->profileGUID = NV_ENC_H264_PROFILE_BASELINE_GUID;
|
2023-09-02 14:57:41 +02:00
|
|
|
avctx->profile = AV_PROFILE_H264_BASELINE;
|
2016-05-20 16:49:24 +02:00
|
|
|
break;
|
2016-05-25 16:26:25 +02:00
|
|
|
case NV_ENC_H264_PROFILE_MAIN:
|
2016-05-25 16:05:50 +02:00
|
|
|
cc->profileGUID = NV_ENC_H264_PROFILE_MAIN_GUID;
|
2023-09-02 14:57:41 +02:00
|
|
|
avctx->profile = AV_PROFILE_H264_MAIN;
|
2016-05-20 16:49:24 +02:00
|
|
|
break;
|
2016-05-25 16:26:25 +02:00
|
|
|
case NV_ENC_H264_PROFILE_HIGH:
|
2016-05-25 16:05:50 +02:00
|
|
|
cc->profileGUID = NV_ENC_H264_PROFILE_HIGH_GUID;
|
2023-09-02 14:57:41 +02:00
|
|
|
avctx->profile = AV_PROFILE_H264_HIGH;
|
2016-05-25 16:26:25 +02:00
|
|
|
break;
|
|
|
|
case NV_ENC_H264_PROFILE_HIGH_444P:
|
2016-05-25 16:05:50 +02:00
|
|
|
cc->profileGUID = NV_ENC_H264_PROFILE_HIGH_444_GUID;
|
2023-09-02 14:57:41 +02:00
|
|
|
avctx->profile = AV_PROFILE_H264_HIGH_444_PREDICTIVE;
|
2016-05-25 16:26:25 +02:00
|
|
|
break;
|
2016-05-20 16:49:24 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// force setting profile as high444p if input is AV_PIX_FMT_YUV444P
|
2021-03-30 22:08:49 +02:00
|
|
|
if (IS_YUV444(ctx->data_pix_fmt)) {
|
2016-05-25 16:05:50 +02:00
|
|
|
cc->profileGUID = NV_ENC_H264_PROFILE_HIGH_444_GUID;
|
2023-09-02 14:57:41 +02:00
|
|
|
avctx->profile = AV_PROFILE_H264_HIGH_444_PREDICTIVE;
|
2014-11-30 01:04:37 +02:00
|
|
|
}
|
|
|
|
|
2023-09-02 14:57:41 +02:00
|
|
|
h264->chromaFormatIDC = avctx->profile == AV_PROFILE_H264_HIGH_444_PREDICTIVE ? 3 : 1;
|
2016-05-20 16:49:24 +02:00
|
|
|
|
2016-05-25 17:00:52 +02:00
|
|
|
h264->level = ctx->level;
|
2016-05-20 16:49:24 +02:00
|
|
|
|
2024-03-31 18:39:49 +02:00
|
|
|
#ifdef NVENC_HAVE_NEW_BIT_DEPTH_API
|
|
|
|
h264->inputBitDepth = h264->outputBitDepth =
|
|
|
|
IS_10BIT(ctx->data_pix_fmt) ? NV_ENC_BIT_DEPTH_10 : NV_ENC_BIT_DEPTH_8;
|
|
|
|
#endif
|
|
|
|
|
2017-08-30 21:06:25 +02:00
|
|
|
if (ctx->coder >= 0)
|
|
|
|
h264->entropyCodingMode = ctx->coder;
|
|
|
|
|
2018-04-11 14:22:20 +02:00
|
|
|
#ifdef NVENC_HAVE_BFRAME_REF_MODE
|
2022-11-02 20:02:56 +02:00
|
|
|
if (ctx->b_ref_mode >= 0)
|
|
|
|
h264->useBFramesAsRef = ctx->b_ref_mode;
|
2018-04-11 14:22:20 +02:00
|
|
|
#endif
|
|
|
|
|
2019-09-27 17:56:11 +02:00
|
|
|
#ifdef NVENC_HAVE_MULTIPLE_REF_FRAMES
|
|
|
|
h264->numRefL0 = avctx->refs;
|
|
|
|
h264->numRefL1 = avctx->refs;
|
|
|
|
#endif
|
|
|
|
|
2016-05-20 16:49:24 +02:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static av_cold int nvenc_setup_hevc_config(AVCodecContext *avctx)
|
|
|
|
{
|
2016-05-25 16:05:50 +02:00
|
|
|
NvencContext *ctx = avctx->priv_data;
|
|
|
|
NV_ENC_CONFIG *cc = &ctx->encode_config;
|
|
|
|
NV_ENC_CONFIG_HEVC *hevc = &cc->encodeCodecConfig.hevcConfig;
|
|
|
|
NV_ENC_CONFIG_HEVC_VUI_PARAMETERS *vui = &hevc->hevcVUIParameters;
|
2016-05-20 16:49:24 +02:00
|
|
|
|
2022-08-06 20:58:48 +02:00
|
|
|
const AVPixFmtDescriptor *pixdesc = av_pix_fmt_desc_get(ctx->data_pix_fmt);
|
|
|
|
|
|
|
|
if ((pixdesc->flags & AV_PIX_FMT_FLAG_RGB) && !IS_GBRP(ctx->data_pix_fmt)) {
|
|
|
|
vui->colourMatrix = AVCOL_SPC_BT470BG;
|
|
|
|
vui->colourPrimaries = avctx->color_primaries;
|
|
|
|
vui->transferCharacteristics = avctx->color_trc;
|
|
|
|
vui->videoFullRangeFlag = 0;
|
|
|
|
} else {
|
|
|
|
vui->colourMatrix = IS_GBRP(ctx->data_pix_fmt) ? AVCOL_SPC_RGB : avctx->colorspace;
|
|
|
|
vui->colourPrimaries = avctx->color_primaries;
|
|
|
|
vui->transferCharacteristics = avctx->color_trc;
|
|
|
|
vui->videoFullRangeFlag = (avctx->color_range == AVCOL_RANGE_JPEG
|
|
|
|
|| ctx->data_pix_fmt == AV_PIX_FMT_YUVJ420P || ctx->data_pix_fmt == AV_PIX_FMT_YUVJ422P || ctx->data_pix_fmt == AV_PIX_FMT_YUVJ444P);
|
|
|
|
}
|
2016-05-20 16:49:24 +02:00
|
|
|
|
2016-05-25 16:05:50 +02:00
|
|
|
vui->colourDescriptionPresentFlag =
|
2021-03-30 22:08:49 +02:00
|
|
|
(vui->colourMatrix != 2 || vui->colourPrimaries != 2 || vui->transferCharacteristics != 2);
|
2016-05-20 16:49:24 +02:00
|
|
|
|
2016-05-25 16:05:50 +02:00
|
|
|
vui->videoSignalTypePresentFlag =
|
|
|
|
(vui->colourDescriptionPresentFlag
|
|
|
|
|| vui->videoFormat != 5
|
|
|
|
|| vui->videoFullRangeFlag != 0);
|
2016-05-20 16:49:24 +02:00
|
|
|
|
2023-07-27 04:26:23 +02:00
|
|
|
if (ctx->max_slice_size > 0) {
|
|
|
|
hevc->sliceMode = 1;
|
|
|
|
hevc->sliceModeData = ctx->max_slice_size;
|
|
|
|
} else {
|
|
|
|
hevc->sliceMode = 3;
|
|
|
|
hevc->sliceModeData = avctx->slices > 0 ? avctx->slices : 1;
|
|
|
|
}
|
2016-05-20 16:49:24 +02:00
|
|
|
|
2021-09-06 04:01:58 +02:00
|
|
|
if (ctx->intra_refresh) {
|
|
|
|
hevc->enableIntraRefresh = 1;
|
2023-06-22 12:18:19 +02:00
|
|
|
hevc->intraRefreshPeriod = cc->gopLength;
|
|
|
|
hevc->intraRefreshCnt = cc->gopLength - 1;
|
2023-07-06 14:00:48 +02:00
|
|
|
cc->gopLength = NVENC_INFINITE_GOPLENGTH;
|
2021-09-02 12:38:57 +02:00
|
|
|
#ifdef NVENC_HAVE_SINGLE_SLICE_INTRA_REFRESH
|
|
|
|
hevc->singleSliceIntraRefresh = ctx->single_slice_intra_refresh;
|
|
|
|
#endif
|
2021-09-06 04:01:58 +02:00
|
|
|
}
|
|
|
|
|
2021-09-02 12:38:58 +02:00
|
|
|
#ifdef NVENC_HAVE_HEVC_CONSTRAINED_ENCODING
|
|
|
|
if (ctx->constrained_encoding)
|
|
|
|
hevc->enableConstrainedEncoding = 1;
|
|
|
|
#endif
|
|
|
|
|
2016-05-25 16:05:50 +02:00
|
|
|
hevc->disableSPSPPS = (avctx->flags & AV_CODEC_FLAG_GLOBAL_HEADER) ? 1 : 0;
|
2016-05-25 18:39:54 +02:00
|
|
|
hevc->repeatSPSPPS = (avctx->flags & AV_CODEC_FLAG_GLOBAL_HEADER) ? 0 : 1;
|
2016-12-30 23:02:42 +02:00
|
|
|
hevc->outputAUD = ctx->aud;
|
2016-05-25 18:39:54 +02:00
|
|
|
|
2019-09-27 17:55:23 +02:00
|
|
|
if (ctx->dpb_size >= 0) {
|
2016-05-25 18:39:54 +02:00
|
|
|
/* 0 means "let the hardware decide" */
|
2019-09-27 17:55:23 +02:00
|
|
|
hevc->maxNumRefFramesInDPB = ctx->dpb_size;
|
2016-05-25 18:39:54 +02:00
|
|
|
}
|
2021-09-06 04:01:58 +02:00
|
|
|
|
2023-07-06 21:57:38 +02:00
|
|
|
hevc->idrPeriod = cc->gopLength;
|
2016-05-20 16:49:24 +02:00
|
|
|
|
2016-05-25 18:39:54 +02:00
|
|
|
if (IS_CBR(cc->rcParams.rateControlMode)) {
|
|
|
|
hevc->outputBufferingPeriodSEI = 1;
|
|
|
|
}
|
2016-05-20 16:49:24 +02:00
|
|
|
|
2017-09-02 15:39:24 +02:00
|
|
|
hevc->outputPictureTimingSEI = 1;
|
|
|
|
|
2017-03-21 00:04:28 +02:00
|
|
|
switch (ctx->profile) {
|
2016-08-25 17:18:03 +02:00
|
|
|
case NV_ENC_HEVC_PROFILE_MAIN:
|
|
|
|
cc->profileGUID = NV_ENC_HEVC_PROFILE_MAIN_GUID;
|
2023-09-02 14:57:41 +02:00
|
|
|
avctx->profile = AV_PROFILE_HEVC_MAIN;
|
2016-08-25 17:18:03 +02:00
|
|
|
break;
|
|
|
|
case NV_ENC_HEVC_PROFILE_MAIN_10:
|
|
|
|
cc->profileGUID = NV_ENC_HEVC_PROFILE_MAIN10_GUID;
|
2023-09-02 14:57:41 +02:00
|
|
|
avctx->profile = AV_PROFILE_HEVC_MAIN_10;
|
2016-08-25 17:18:03 +02:00
|
|
|
break;
|
2016-09-28 14:21:03 +02:00
|
|
|
case NV_ENC_HEVC_PROFILE_REXT:
|
|
|
|
cc->profileGUID = NV_ENC_HEVC_PROFILE_FREXT_GUID;
|
2023-09-02 14:57:41 +02:00
|
|
|
avctx->profile = AV_PROFILE_HEVC_REXT;
|
2016-09-28 14:21:03 +02:00
|
|
|
break;
|
2016-08-25 17:18:03 +02:00
|
|
|
}
|
|
|
|
|
2024-04-19 10:38:51 +02:00
|
|
|
// force setting profile as main10 if input is 10 bit or if it should be encoded as 10 bit
|
|
|
|
if (IS_10BIT(ctx->data_pix_fmt) || ctx->highbitdepth) {
|
2016-08-25 17:18:03 +02:00
|
|
|
cc->profileGUID = NV_ENC_HEVC_PROFILE_MAIN10_GUID;
|
2023-09-02 14:57:41 +02:00
|
|
|
avctx->profile = AV_PROFILE_HEVC_MAIN_10;
|
2016-08-25 17:18:03 +02:00
|
|
|
}
|
|
|
|
|
2016-09-28 14:21:03 +02:00
|
|
|
// force setting profile as rext if input is yuv444
|
|
|
|
if (IS_YUV444(ctx->data_pix_fmt)) {
|
|
|
|
cc->profileGUID = NV_ENC_HEVC_PROFILE_FREXT_GUID;
|
2023-09-02 14:57:41 +02:00
|
|
|
avctx->profile = AV_PROFILE_HEVC_REXT;
|
2016-09-28 14:21:03 +02:00
|
|
|
}
|
|
|
|
|
2016-08-25 17:18:03 +02:00
|
|
|
hevc->chromaFormatIDC = IS_YUV444(ctx->data_pix_fmt) ? 3 : 1;
|
|
|
|
|
2024-03-31 18:39:49 +02:00
|
|
|
#ifdef NVENC_HAVE_NEW_BIT_DEPTH_API
|
2024-04-19 10:38:51 +02:00
|
|
|
hevc->inputBitDepth = IS_10BIT(ctx->data_pix_fmt) ? NV_ENC_BIT_DEPTH_10 : NV_ENC_BIT_DEPTH_8;
|
|
|
|
hevc->outputBitDepth = (IS_10BIT(ctx->data_pix_fmt) || ctx->highbitdepth) ? NV_ENC_BIT_DEPTH_10 : NV_ENC_BIT_DEPTH_8;
|
2024-03-31 18:39:49 +02:00
|
|
|
#else
|
2016-08-25 17:18:03 +02:00
|
|
|
hevc->pixelBitDepthMinus8 = IS_10BIT(ctx->data_pix_fmt) ? 2 : 0;
|
2024-03-31 18:39:49 +02:00
|
|
|
#endif
|
2016-05-20 16:49:24 +02:00
|
|
|
|
2016-05-25 17:00:52 +02:00
|
|
|
hevc->level = ctx->level;
|
2016-05-20 16:49:24 +02:00
|
|
|
|
2016-05-25 17:06:02 +02:00
|
|
|
hevc->tier = ctx->tier;
|
2016-05-20 16:49:24 +02:00
|
|
|
|
2019-02-14 14:20:25 +02:00
|
|
|
#ifdef NVENC_HAVE_HEVC_BFRAME_REF_MODE
|
2022-11-02 20:02:56 +02:00
|
|
|
if (ctx->b_ref_mode >= 0)
|
|
|
|
hevc->useBFramesAsRef = ctx->b_ref_mode;
|
2019-02-14 14:20:25 +02:00
|
|
|
#endif
|
|
|
|
|
2019-09-27 17:56:11 +02:00
|
|
|
#ifdef NVENC_HAVE_MULTIPLE_REF_FRAMES
|
|
|
|
hevc->numRefL0 = avctx->refs;
|
|
|
|
hevc->numRefL1 = avctx->refs;
|
|
|
|
#endif
|
|
|
|
|
2024-03-31 20:10:45 +02:00
|
|
|
#ifdef NVENC_HAVE_TEMPORAL_FILTER
|
|
|
|
if (ctx->tf_level >= 0) {
|
|
|
|
hevc->tfLevel = ctx->tf_level;
|
|
|
|
|
|
|
|
switch (ctx->tf_level)
|
|
|
|
{
|
|
|
|
case NV_ENC_TEMPORAL_FILTER_LEVEL_0:
|
|
|
|
case NV_ENC_TEMPORAL_FILTER_LEVEL_4:
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
av_log(avctx, AV_LOG_ERROR, "Invalid temporal filtering level.\n");
|
|
|
|
return AVERROR(EINVAL);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (ctx->encode_config.frameIntervalP < 5)
|
|
|
|
av_log(avctx, AV_LOG_WARNING, "Temporal filtering needs at least 4 B-Frames (-bf 4).\n");
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2016-05-20 16:49:24 +02:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2022-11-05 22:17:37 +02:00
|
|
|
#if CONFIG_AV1_NVENC_ENCODER
|
|
|
|
static av_cold int nvenc_setup_av1_config(AVCodecContext *avctx)
|
|
|
|
{
|
|
|
|
NvencContext *ctx = avctx->priv_data;
|
|
|
|
NV_ENC_CONFIG *cc = &ctx->encode_config;
|
|
|
|
NV_ENC_CONFIG_AV1 *av1 = &cc->encodeCodecConfig.av1Config;
|
|
|
|
|
|
|
|
const AVPixFmtDescriptor *pixdesc = av_pix_fmt_desc_get(ctx->data_pix_fmt);
|
|
|
|
|
|
|
|
if ((pixdesc->flags & AV_PIX_FMT_FLAG_RGB) && !IS_GBRP(ctx->data_pix_fmt)) {
|
|
|
|
av1->matrixCoefficients = AVCOL_SPC_BT470BG;
|
|
|
|
av1->colorPrimaries = avctx->color_primaries;
|
|
|
|
av1->transferCharacteristics = avctx->color_trc;
|
|
|
|
av1->colorRange = 0;
|
|
|
|
} else {
|
|
|
|
av1->matrixCoefficients = IS_GBRP(ctx->data_pix_fmt) ? AVCOL_SPC_RGB : avctx->colorspace;
|
|
|
|
av1->colorPrimaries = avctx->color_primaries;
|
|
|
|
av1->transferCharacteristics = avctx->color_trc;
|
|
|
|
av1->colorRange = (avctx->color_range == AVCOL_RANGE_JPEG
|
|
|
|
|| ctx->data_pix_fmt == AV_PIX_FMT_YUVJ420P || ctx->data_pix_fmt == AV_PIX_FMT_YUVJ422P || ctx->data_pix_fmt == AV_PIX_FMT_YUVJ444P);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (IS_YUV444(ctx->data_pix_fmt)) {
|
2022-11-10 16:26:43 +02:00
|
|
|
av_log(avctx, AV_LOG_ERROR, "AV1 High Profile not supported, required for 4:4:4 encoding\n");
|
|
|
|
return AVERROR(ENOTSUP);
|
2022-11-05 22:17:37 +02:00
|
|
|
} else {
|
|
|
|
cc->profileGUID = NV_ENC_AV1_PROFILE_MAIN_GUID;
|
2023-09-02 14:57:41 +02:00
|
|
|
avctx->profile = AV_PROFILE_AV1_MAIN;
|
2022-11-05 22:17:37 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
if (ctx->dpb_size >= 0) {
|
|
|
|
/* 0 means "let the hardware decide" */
|
|
|
|
av1->maxNumRefFramesInDPB = ctx->dpb_size;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (ctx->intra_refresh) {
|
|
|
|
av1->enableIntraRefresh = 1;
|
2023-06-22 12:18:19 +02:00
|
|
|
av1->intraRefreshPeriod = cc->gopLength;
|
|
|
|
av1->intraRefreshCnt = cc->gopLength - 1;
|
2023-07-06 14:00:48 +02:00
|
|
|
cc->gopLength = NVENC_INFINITE_GOPLENGTH;
|
2022-11-05 22:17:37 +02:00
|
|
|
}
|
|
|
|
|
2023-07-06 21:57:38 +02:00
|
|
|
av1->idrPeriod = cc->gopLength;
|
|
|
|
|
2022-11-05 22:17:37 +02:00
|
|
|
if (IS_CBR(cc->rcParams.rateControlMode)) {
|
|
|
|
av1->enableBitstreamPadding = 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (ctx->tile_cols >= 0)
|
|
|
|
av1->numTileColumns = ctx->tile_cols;
|
|
|
|
if (ctx->tile_rows >= 0)
|
|
|
|
av1->numTileRows = ctx->tile_rows;
|
|
|
|
|
|
|
|
av1->outputAnnexBFormat = 0;
|
|
|
|
|
|
|
|
av1->level = ctx->level;
|
|
|
|
av1->tier = ctx->tier;
|
|
|
|
|
|
|
|
av1->enableTimingInfo = ctx->timing_info;
|
|
|
|
|
|
|
|
/* mp4 encapsulation requires sequence headers to be present on all keyframes for AV1 */
|
|
|
|
av1->disableSeqHdr = 0;
|
|
|
|
av1->repeatSeqHdr = 1;
|
|
|
|
|
|
|
|
av1->chromaFormatIDC = IS_YUV444(ctx->data_pix_fmt) ? 3 : 1;
|
|
|
|
|
2024-03-31 18:39:49 +02:00
|
|
|
#ifdef NVENC_HAVE_NEW_BIT_DEPTH_API
|
|
|
|
av1->inputBitDepth = IS_10BIT(ctx->data_pix_fmt) ? NV_ENC_BIT_DEPTH_10 : NV_ENC_BIT_DEPTH_8;
|
|
|
|
av1->outputBitDepth = (IS_10BIT(ctx->data_pix_fmt) || ctx->highbitdepth) ? NV_ENC_BIT_DEPTH_10 : NV_ENC_BIT_DEPTH_8;
|
|
|
|
#else
|
2022-11-05 22:17:37 +02:00
|
|
|
av1->inputPixelBitDepthMinus8 = IS_10BIT(ctx->data_pix_fmt) ? 2 : 0;
|
|
|
|
av1->pixelBitDepthMinus8 = (IS_10BIT(ctx->data_pix_fmt) || ctx->highbitdepth) ? 2 : 0;
|
2024-03-31 18:39:49 +02:00
|
|
|
#endif
|
2022-11-05 22:17:37 +02:00
|
|
|
|
|
|
|
if (ctx->b_ref_mode >= 0)
|
|
|
|
av1->useBFramesAsRef = ctx->b_ref_mode;
|
|
|
|
|
|
|
|
av1->numFwdRefs = avctx->refs;
|
|
|
|
av1->numBwdRefs = avctx->refs;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2016-05-25 16:05:50 +02:00
|
|
|
static av_cold int nvenc_setup_codec_config(AVCodecContext *avctx)
|
2016-05-20 16:49:24 +02:00
|
|
|
{
|
|
|
|
switch (avctx->codec->id) {
|
|
|
|
case AV_CODEC_ID_H264:
|
2016-05-25 16:05:50 +02:00
|
|
|
return nvenc_setup_h264_config(avctx);
|
|
|
|
case AV_CODEC_ID_HEVC:
|
2016-05-20 16:49:24 +02:00
|
|
|
return nvenc_setup_hevc_config(avctx);
|
2022-11-05 22:17:37 +02:00
|
|
|
#if CONFIG_AV1_NVENC_ENCODER
|
|
|
|
case AV_CODEC_ID_AV1:
|
|
|
|
return nvenc_setup_av1_config(avctx);
|
|
|
|
#endif
|
2016-05-20 16:49:24 +02:00
|
|
|
/* Earlier switch/case will return if unknown codec is passed. */
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2017-02-12 20:53:58 +02:00
|
|
|
static void compute_dar(AVCodecContext *avctx, int *dw, int *dh) {
|
|
|
|
int sw, sh;
|
|
|
|
|
|
|
|
sw = avctx->width;
|
|
|
|
sh = avctx->height;
|
|
|
|
|
2022-11-10 14:05:59 +02:00
|
|
|
#if CONFIG_AV1_NVENC_ENCODER
|
|
|
|
if (avctx->codec->id == AV_CODEC_ID_AV1) {
|
|
|
|
/* For AV1 we actually need to calculate the render width/height, not the dar */
|
|
|
|
if (avctx->sample_aspect_ratio.num > 0 && avctx->sample_aspect_ratio.den > 0
|
|
|
|
&& avctx->sample_aspect_ratio.num != avctx->sample_aspect_ratio.den)
|
|
|
|
{
|
|
|
|
if (avctx->sample_aspect_ratio.num > avctx->sample_aspect_ratio.den) {
|
|
|
|
sw = av_rescale(sw, avctx->sample_aspect_ratio.num, avctx->sample_aspect_ratio.den);
|
|
|
|
} else {
|
|
|
|
sh = av_rescale(sh, avctx->sample_aspect_ratio.den, avctx->sample_aspect_ratio.num);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
*dw = sw;
|
|
|
|
*dh = sh;
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2017-02-12 20:53:58 +02:00
|
|
|
if (avctx->sample_aspect_ratio.num > 0 && avctx->sample_aspect_ratio.den > 0) {
|
|
|
|
sw *= avctx->sample_aspect_ratio.num;
|
|
|
|
sh *= avctx->sample_aspect_ratio.den;
|
|
|
|
}
|
|
|
|
|
|
|
|
av_reduce(dw, dh, sw, sh, 1024 * 1024);
|
|
|
|
}
|
|
|
|
|
2016-05-20 16:49:24 +02:00
|
|
|
static av_cold int nvenc_setup_encoder(AVCodecContext *avctx)
|
|
|
|
{
|
|
|
|
NvencContext *ctx = avctx->priv_data;
|
|
|
|
NvencDynLoadFunctions *dl_fn = &ctx->nvenc_dload_funcs;
|
|
|
|
NV_ENCODE_API_FUNCTION_LIST *p_nvenc = &dl_fn->nvenc_funcs;
|
|
|
|
|
|
|
|
NV_ENC_PRESET_CONFIG preset_config = { 0 };
|
|
|
|
NVENCSTATUS nv_status = NV_ENC_SUCCESS;
|
|
|
|
AVCPBProperties *cpb_props;
|
|
|
|
int res = 0;
|
|
|
|
int dw, dh;
|
|
|
|
|
|
|
|
ctx->encode_config.version = NV_ENC_CONFIG_VER;
|
|
|
|
ctx->init_encode_params.version = NV_ENC_INITIALIZE_PARAMS_VER;
|
|
|
|
|
2016-05-25 16:05:50 +02:00
|
|
|
ctx->init_encode_params.encodeHeight = avctx->height;
|
|
|
|
ctx->init_encode_params.encodeWidth = avctx->width;
|
|
|
|
|
|
|
|
ctx->init_encode_params.encodeConfig = &ctx->encode_config;
|
|
|
|
|
|
|
|
preset_config.version = NV_ENC_PRESET_CONFIG_VER;
|
|
|
|
preset_config.presetCfg.version = NV_ENC_CONFIG_VER;
|
2015-03-24 06:34:59 +02:00
|
|
|
|
2020-03-19 10:35:29 +02:00
|
|
|
#ifdef NVENC_HAVE_NEW_PRESETS
|
2020-10-29 22:59:37 +02:00
|
|
|
ctx->init_encode_params.tuningInfo = ctx->tuning_info;
|
2020-03-19 10:35:29 +02:00
|
|
|
|
2021-04-18 11:17:54 +02:00
|
|
|
if (ctx->flags & NVENC_LOSSLESS)
|
|
|
|
ctx->init_encode_params.tuningInfo = NV_ENC_TUNING_INFO_LOSSLESS;
|
|
|
|
else if (ctx->flags & NVENC_LOWLATENCY)
|
2020-10-29 22:59:37 +02:00
|
|
|
ctx->init_encode_params.tuningInfo = NV_ENC_TUNING_INFO_LOW_LATENCY;
|
2020-10-21 18:45:52 +02:00
|
|
|
|
2020-10-29 22:59:37 +02:00
|
|
|
nv_status = p_nvenc->nvEncGetEncodePresetConfigEx(ctx->nvencoder,
|
|
|
|
ctx->init_encode_params.encodeGUID,
|
|
|
|
ctx->init_encode_params.presetGUID,
|
|
|
|
ctx->init_encode_params.tuningInfo,
|
|
|
|
&preset_config);
|
|
|
|
#else
|
|
|
|
nv_status = p_nvenc->nvEncGetEncodePresetConfig(ctx->nvencoder,
|
|
|
|
ctx->init_encode_params.encodeGUID,
|
|
|
|
ctx->init_encode_params.presetGUID,
|
|
|
|
&preset_config);
|
|
|
|
#endif
|
2016-05-25 16:05:50 +02:00
|
|
|
if (nv_status != NV_ENC_SUCCESS)
|
|
|
|
return nvenc_print_error(avctx, nv_status, "Cannot get the preset configuration");
|
2014-11-30 01:04:37 +02:00
|
|
|
|
2016-05-25 16:05:50 +02:00
|
|
|
memcpy(&ctx->encode_config, &preset_config.presetCfg, sizeof(ctx->encode_config));
|
|
|
|
|
|
|
|
ctx->encode_config.version = NV_ENC_CONFIG_VER;
|
2015-01-26 14:28:22 +02:00
|
|
|
|
2017-02-12 20:53:58 +02:00
|
|
|
compute_dar(avctx, &dw, &dh);
|
2016-11-27 02:46:06 +02:00
|
|
|
ctx->init_encode_params.darHeight = dh;
|
|
|
|
ctx->init_encode_params.darWidth = dw;
|
2015-01-26 14:28:22 +02:00
|
|
|
|
2020-05-14 20:15:33 +02:00
|
|
|
if (avctx->framerate.num > 0 && avctx->framerate.den > 0) {
|
|
|
|
ctx->init_encode_params.frameRateNum = avctx->framerate.num;
|
|
|
|
ctx->init_encode_params.frameRateDen = avctx->framerate.den;
|
|
|
|
} else {
|
|
|
|
ctx->init_encode_params.frameRateNum = avctx->time_base.den;
|
2023-05-04 11:50:48 +02:00
|
|
|
FF_DISABLE_DEPRECATION_WARNINGS
|
|
|
|
ctx->init_encode_params.frameRateDen = avctx->time_base.num
|
|
|
|
#if FF_API_TICKS_PER_FRAME
|
|
|
|
* avctx->ticks_per_frame
|
|
|
|
#endif
|
|
|
|
;
|
|
|
|
FF_ENABLE_DEPRECATION_WARNINGS
|
2020-05-14 20:15:33 +02:00
|
|
|
}
|
2014-11-30 01:04:37 +02:00
|
|
|
|
2024-03-31 21:26:15 +02:00
|
|
|
#ifdef NVENC_HAVE_UNIDIR_B
|
|
|
|
ctx->init_encode_params.enableUniDirectionalB = ctx->unidir_b;
|
|
|
|
#endif
|
|
|
|
|
2014-11-30 01:04:37 +02:00
|
|
|
ctx->init_encode_params.enableEncodeAsync = 0;
|
|
|
|
ctx->init_encode_params.enablePTD = 1;
|
|
|
|
|
2020-03-19 10:35:29 +02:00
|
|
|
#ifdef NVENC_HAVE_NEW_PRESETS
|
|
|
|
/* If lookahead isn't set from CLI, use value from preset.
|
|
|
|
* P6 & P7 presets may enable lookahead for better quality.
|
|
|
|
* */
|
|
|
|
if (ctx->rc_lookahead == 0 && ctx->encode_config.rcParams.enableLookahead)
|
|
|
|
ctx->rc_lookahead = ctx->encode_config.rcParams.lookaheadDepth;
|
|
|
|
#endif
|
|
|
|
|
2017-05-09 16:24:54 +02:00
|
|
|
if (ctx->weighted_pred == 1)
|
|
|
|
ctx->init_encode_params.enableWeightedPrediction = 1;
|
|
|
|
|
2024-04-12 22:08:12 +02:00
|
|
|
#ifdef NVENC_HAVE_SPLIT_FRAME_ENCODING
|
|
|
|
ctx->init_encode_params.splitEncodeMode = ctx->split_encode_mode;
|
|
|
|
|
|
|
|
if (ctx->split_encode_mode != NV_ENC_SPLIT_DISABLE_MODE) {
|
|
|
|
if (avctx->codec->id == AV_CODEC_ID_HEVC && ctx->weighted_pred == 1)
|
|
|
|
av_log(avctx, AV_LOG_WARNING, "Split encoding not supported with weighted prediction enabled.\n");
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2016-12-30 23:04:31 +02:00
|
|
|
if (ctx->bluray_compat) {
|
|
|
|
ctx->aud = 1;
|
2019-09-27 17:55:23 +02:00
|
|
|
ctx->dpb_size = FFMIN(FFMAX(avctx->refs, 0), 6);
|
2016-12-30 23:04:31 +02:00
|
|
|
avctx->max_b_frames = FFMIN(avctx->max_b_frames, 3);
|
|
|
|
switch (avctx->codec->id) {
|
|
|
|
case AV_CODEC_ID_H264:
|
|
|
|
/* maximum level depends on used resolution */
|
|
|
|
break;
|
|
|
|
case AV_CODEC_ID_HEVC:
|
|
|
|
ctx->level = NV_ENC_LEVEL_HEVC_51;
|
|
|
|
ctx->tier = NV_ENC_TIER_HEVC_HIGH;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2015-01-26 14:28:21 +02:00
|
|
|
if (avctx->gop_size > 0) {
|
2023-06-22 12:18:19 +02:00
|
|
|
// only overwrite preset if a GOP size was selected as input
|
2014-11-30 01:04:37 +02:00
|
|
|
ctx->encode_config.gopLength = avctx->gop_size;
|
2016-05-20 16:49:24 +02:00
|
|
|
} else if (avctx->gop_size == 0) {
|
|
|
|
ctx->encode_config.frameIntervalP = 0;
|
|
|
|
ctx->encode_config.gopLength = 1;
|
2014-11-30 01:04:37 +02:00
|
|
|
}
|
|
|
|
|
2023-06-22 12:18:19 +02:00
|
|
|
if (avctx->max_b_frames >= 0 && ctx->encode_config.gopLength > 1) {
|
|
|
|
/* 0 is intra-only, 1 is I/P only, 2 is one B-Frame, 3 two B-frames, and so on. */
|
|
|
|
ctx->encode_config.frameIntervalP = avctx->max_b_frames + 1;
|
|
|
|
}
|
|
|
|
|
2021-09-02 12:38:57 +02:00
|
|
|
/* force to enable intra refresh */
|
|
|
|
if(ctx->single_slice_intra_refresh)
|
|
|
|
ctx->intra_refresh = 1;
|
|
|
|
|
avcodec/nvenc: better surface allocation alghoritm, fix rc_lookahead
User selectable surfaces are not working correctly, if you set number of
surfaces on cmdline, it will always use minimum 32 or 48 depends on
selected resolution, but in nvenc it is not necessary to use so many
surfaces.
So from now you can define as low as 1 surface and nvenc will still
work, it will ofcourse lower GPU memory usage by 95% and async_delay to zero
That was the easy part, now littlebit more...
Next part of this patch is to always prefer rc_lookahead to be more
important for number of surfaces, than user defined surfaces value.
Maximum rc_lookahead from nvidia documentation is 32, but could increase
in future generations so there is no limit for this yet. Value
async_depth is still accepted and prefered over rc_lookahead.
There were also bug when you request more than rc_lookahead > 31, it
will always set maximum 31, because surface numbers recalculation was
after setting lookahead, which is now fixed.
Results:
If you set -rc_lookahead 32 and -bf 3 it will now use only 40 surfaces
and lower GPU memory usage by 20%, also it will now increase PSNR by 0.012dB
Two more comments:
1. from my internal test, i don't understand addition of 4 more surfaces
when lookahead is calculated, i didn't used this and everything works as
with those 4 more extra surfaces, does anybody know what is going on
there? I looks like it was used for B frames which are calculated
separately, because B frames maximum is 4.
2. rc_lookahead is defined default to -1, but in test condition if
(ctx->rc_lookahead) which sets lookahead it will be always true, i don't
know if this is intended behavior, so in default behavior is lookahead
always on!
This is default condition when rc_lokkahead is -1 (not defined on
cmdline), whis is maybe something that is not intended:
ctx->encode_config.rcParams.enableLookahead = 1;
ctx->encode_config.rcParams.lookaheadDepth = 0;
ctx->encode_config.rcParams.disableIadapt = 0;
ctx->encode_config.rcParams.disableBadapt = 0;
Signed-off-by: Timo Rothenpieler <timo@rothenpieler.org>
2016-11-21 13:17:43 +02:00
|
|
|
nvenc_recalc_surfaces(avctx);
|
|
|
|
|
2024-03-31 20:52:27 +02:00
|
|
|
res = nvenc_setup_rate_control(avctx);
|
|
|
|
if (res < 0)
|
|
|
|
return res;
|
2014-11-30 01:04:37 +02:00
|
|
|
|
2015-07-27 21:14:31 +02:00
|
|
|
if (avctx->flags & AV_CODEC_FLAG_INTERLACED_DCT) {
|
2014-11-30 01:04:37 +02:00
|
|
|
ctx->encode_config.frameFieldMode = NV_ENC_PARAMS_FRAME_FIELD_MODE_FIELD;
|
|
|
|
} else {
|
|
|
|
ctx->encode_config.frameFieldMode = NV_ENC_PARAMS_FRAME_FIELD_MODE_FRAME;
|
|
|
|
}
|
|
|
|
|
2016-05-25 16:05:50 +02:00
|
|
|
res = nvenc_setup_codec_config(avctx);
|
2016-05-20 16:49:24 +02:00
|
|
|
if (res)
|
|
|
|
return res;
|
2016-03-04 11:00:48 +02:00
|
|
|
|
2017-11-11 17:13:24 +02:00
|
|
|
res = nvenc_push_context(avctx);
|
|
|
|
if (res < 0)
|
|
|
|
return res;
|
2017-05-31 04:03:14 +02:00
|
|
|
|
2016-05-20 16:49:24 +02:00
|
|
|
nv_status = p_nvenc->nvEncInitializeEncoder(ctx->nvencoder, &ctx->init_encode_params);
|
2019-09-27 18:30:10 +02:00
|
|
|
if (nv_status != NV_ENC_SUCCESS) {
|
|
|
|
nvenc_pop_context(avctx);
|
|
|
|
return nvenc_print_error(avctx, nv_status, "InitializeEncoder failed");
|
|
|
|
}
|
|
|
|
|
|
|
|
#ifdef NVENC_HAVE_CUSTREAM_PTR
|
|
|
|
if (ctx->cu_context) {
|
|
|
|
nv_status = p_nvenc->nvEncSetIOCudaStreams(ctx->nvencoder, &ctx->cu_stream, &ctx->cu_stream);
|
|
|
|
if (nv_status != NV_ENC_SUCCESS) {
|
|
|
|
nvenc_pop_context(avctx);
|
|
|
|
return nvenc_print_error(avctx, nv_status, "SetIOCudaStreams failed");
|
|
|
|
}
|
|
|
|
}
|
|
|
|
#endif
|
2017-05-31 04:03:14 +02:00
|
|
|
|
2017-11-11 17:13:24 +02:00
|
|
|
res = nvenc_pop_context(avctx);
|
|
|
|
if (res < 0)
|
|
|
|
return res;
|
2017-05-31 04:03:14 +02:00
|
|
|
|
2016-05-20 16:49:24 +02:00
|
|
|
if (ctx->encode_config.frameIntervalP > 1)
|
|
|
|
avctx->has_b_frames = 2;
|
2014-11-30 01:04:37 +02:00
|
|
|
|
2016-05-20 16:49:24 +02:00
|
|
|
if (ctx->encode_config.rcParams.averageBitRate > 0)
|
|
|
|
avctx->bit_rate = ctx->encode_config.rcParams.averageBitRate;
|
2015-12-14 11:27:36 +02:00
|
|
|
|
2023-09-04 14:39:07 +02:00
|
|
|
cpb_props = ff_encode_add_cpb_side_data(avctx);
|
2016-05-20 16:49:24 +02:00
|
|
|
if (!cpb_props)
|
|
|
|
return AVERROR(ENOMEM);
|
|
|
|
cpb_props->max_bitrate = ctx->encode_config.rcParams.maxBitRate;
|
|
|
|
cpb_props->avg_bitrate = avctx->bit_rate;
|
|
|
|
cpb_props->buffer_size = ctx->encode_config.rcParams.vbvBufferSize;
|
2015-04-02 00:04:07 +02:00
|
|
|
|
2016-05-20 16:49:24 +02:00
|
|
|
return 0;
|
|
|
|
}
|
2016-03-30 12:03:59 +02:00
|
|
|
|
2016-11-25 21:11:45 +02:00
|
|
|
static NV_ENC_BUFFER_FORMAT nvenc_map_buffer_format(enum AVPixelFormat pix_fmt)
|
2016-05-20 16:49:24 +02:00
|
|
|
{
|
2016-11-25 21:11:45 +02:00
|
|
|
switch (pix_fmt) {
|
2016-05-20 16:49:24 +02:00
|
|
|
case AV_PIX_FMT_YUV420P:
|
2024-03-31 18:25:15 +02:00
|
|
|
return NV_ENC_BUFFER_FORMAT_YV12;
|
2016-05-20 16:49:24 +02:00
|
|
|
case AV_PIX_FMT_NV12:
|
2024-03-31 18:25:15 +02:00
|
|
|
return NV_ENC_BUFFER_FORMAT_NV12;
|
2016-08-25 17:18:03 +02:00
|
|
|
case AV_PIX_FMT_P010:
|
2018-02-25 19:08:06 +02:00
|
|
|
case AV_PIX_FMT_P016:
|
2016-11-25 21:11:45 +02:00
|
|
|
return NV_ENC_BUFFER_FORMAT_YUV420_10BIT;
|
2021-03-30 22:08:49 +02:00
|
|
|
case AV_PIX_FMT_GBRP:
|
2016-05-20 16:49:24 +02:00
|
|
|
case AV_PIX_FMT_YUV444P:
|
2024-03-31 18:25:15 +02:00
|
|
|
return NV_ENC_BUFFER_FORMAT_YUV444;
|
2021-03-30 22:08:49 +02:00
|
|
|
case AV_PIX_FMT_GBRP16:
|
2016-08-25 17:18:03 +02:00
|
|
|
case AV_PIX_FMT_YUV444P16:
|
2016-11-25 21:11:45 +02:00
|
|
|
return NV_ENC_BUFFER_FORMAT_YUV444_10BIT;
|
2016-09-07 15:35:14 +02:00
|
|
|
case AV_PIX_FMT_0RGB32:
|
2022-07-05 01:58:10 +02:00
|
|
|
case AV_PIX_FMT_RGB32:
|
2016-11-25 21:11:45 +02:00
|
|
|
return NV_ENC_BUFFER_FORMAT_ARGB;
|
2016-09-07 15:35:14 +02:00
|
|
|
case AV_PIX_FMT_0BGR32:
|
2022-07-05 01:58:10 +02:00
|
|
|
case AV_PIX_FMT_BGR32:
|
2016-11-25 21:11:45 +02:00
|
|
|
return NV_ENC_BUFFER_FORMAT_ABGR;
|
2022-07-05 01:58:10 +02:00
|
|
|
case AV_PIX_FMT_X2RGB10:
|
|
|
|
return NV_ENC_BUFFER_FORMAT_ARGB10;
|
|
|
|
case AV_PIX_FMT_X2BGR10:
|
|
|
|
return NV_ENC_BUFFER_FORMAT_ABGR10;
|
2016-05-20 16:49:24 +02:00
|
|
|
default:
|
2016-11-25 21:11:45 +02:00
|
|
|
return NV_ENC_BUFFER_FORMAT_UNDEFINED;
|
2016-05-20 16:49:24 +02:00
|
|
|
}
|
2016-11-25 21:11:45 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
static av_cold int nvenc_alloc_surface(AVCodecContext *avctx, int idx)
|
|
|
|
{
|
|
|
|
NvencContext *ctx = avctx->priv_data;
|
|
|
|
NvencDynLoadFunctions *dl_fn = &ctx->nvenc_dload_funcs;
|
|
|
|
NV_ENCODE_API_FUNCTION_LIST *p_nvenc = &dl_fn->nvenc_funcs;
|
2017-04-25 23:57:56 +02:00
|
|
|
NvencSurface* tmp_surface = &ctx->surfaces[idx];
|
2016-11-25 21:11:45 +02:00
|
|
|
|
|
|
|
NVENCSTATUS nv_status;
|
|
|
|
NV_ENC_CREATE_BITSTREAM_BUFFER allocOut = { 0 };
|
|
|
|
allocOut.version = NV_ENC_CREATE_BITSTREAM_BUFFER_VER;
|
2015-12-14 11:27:36 +02:00
|
|
|
|
2017-11-11 17:51:58 +02:00
|
|
|
if (avctx->pix_fmt == AV_PIX_FMT_CUDA || avctx->pix_fmt == AV_PIX_FMT_D3D11) {
|
2016-05-21 00:08:06 +02:00
|
|
|
ctx->surfaces[idx].in_ref = av_frame_alloc();
|
|
|
|
if (!ctx->surfaces[idx].in_ref)
|
|
|
|
return AVERROR(ENOMEM);
|
|
|
|
} else {
|
|
|
|
NV_ENC_CREATE_INPUT_BUFFER allocSurf = { 0 };
|
2016-11-25 21:11:45 +02:00
|
|
|
|
|
|
|
ctx->surfaces[idx].format = nvenc_map_buffer_format(ctx->data_pix_fmt);
|
|
|
|
if (ctx->surfaces[idx].format == NV_ENC_BUFFER_FORMAT_UNDEFINED) {
|
|
|
|
av_log(avctx, AV_LOG_FATAL, "Invalid input pixel format: %s\n",
|
|
|
|
av_get_pix_fmt_name(ctx->data_pix_fmt));
|
|
|
|
return AVERROR(EINVAL);
|
|
|
|
}
|
|
|
|
|
2016-05-21 00:08:06 +02:00
|
|
|
allocSurf.version = NV_ENC_CREATE_INPUT_BUFFER_VER;
|
2017-05-23 11:24:40 +02:00
|
|
|
allocSurf.width = avctx->width;
|
|
|
|
allocSurf.height = avctx->height;
|
2016-05-21 00:08:06 +02:00
|
|
|
allocSurf.bufferFmt = ctx->surfaces[idx].format;
|
|
|
|
|
|
|
|
nv_status = p_nvenc->nvEncCreateInputBuffer(ctx->nvencoder, &allocSurf);
|
|
|
|
if (nv_status != NV_ENC_SUCCESS) {
|
|
|
|
return nvenc_print_error(avctx, nv_status, "CreateInputBuffer failed");
|
|
|
|
}
|
|
|
|
|
|
|
|
ctx->surfaces[idx].input_surface = allocSurf.inputBuffer;
|
|
|
|
ctx->surfaces[idx].width = allocSurf.width;
|
|
|
|
ctx->surfaces[idx].height = allocSurf.height;
|
2016-05-20 16:49:24 +02:00
|
|
|
}
|
2015-04-02 00:04:07 +02:00
|
|
|
|
2016-05-20 16:49:24 +02:00
|
|
|
nv_status = p_nvenc->nvEncCreateBitstreamBuffer(ctx->nvencoder, &allocOut);
|
|
|
|
if (nv_status != NV_ENC_SUCCESS) {
|
2016-05-20 17:37:00 +02:00
|
|
|
int err = nvenc_print_error(avctx, nv_status, "CreateBitstreamBuffer failed");
|
2017-11-11 17:51:58 +02:00
|
|
|
if (avctx->pix_fmt != AV_PIX_FMT_CUDA && avctx->pix_fmt != AV_PIX_FMT_D3D11)
|
2016-05-21 00:08:06 +02:00
|
|
|
p_nvenc->nvEncDestroyInputBuffer(ctx->nvencoder, ctx->surfaces[idx].input_surface);
|
|
|
|
av_frame_free(&ctx->surfaces[idx].in_ref);
|
2016-05-20 17:37:00 +02:00
|
|
|
return err;
|
2016-05-20 16:49:24 +02:00
|
|
|
}
|
2015-04-04 13:34:14 +02:00
|
|
|
|
2016-05-20 17:37:00 +02:00
|
|
|
ctx->surfaces[idx].output_surface = allocOut.bitstreamBuffer;
|
2015-04-04 13:34:14 +02:00
|
|
|
|
2022-01-06 17:59:49 +02:00
|
|
|
av_fifo_write(ctx->unused_surface_queue, &tmp_surface, 1);
|
2017-04-25 23:57:56 +02:00
|
|
|
|
2016-05-20 16:49:24 +02:00
|
|
|
return 0;
|
|
|
|
}
|
2014-11-30 01:04:37 +02:00
|
|
|
|
2016-05-25 18:57:11 +02:00
|
|
|
static av_cold int nvenc_setup_surfaces(AVCodecContext *avctx)
|
2016-05-20 16:49:24 +02:00
|
|
|
{
|
|
|
|
NvencContext *ctx = avctx->priv_data;
|
2017-11-15 19:33:31 +02:00
|
|
|
int i, res = 0, res2;
|
2014-11-30 01:04:37 +02:00
|
|
|
|
2021-09-14 21:31:53 +02:00
|
|
|
ctx->surfaces = av_calloc(ctx->nb_surfaces, sizeof(*ctx->surfaces));
|
2016-05-29 12:07:34 +02:00
|
|
|
if (!ctx->surfaces)
|
2016-05-20 16:49:24 +02:00
|
|
|
return AVERROR(ENOMEM);
|
2014-11-30 01:04:37 +02:00
|
|
|
|
2023-06-16 21:35:45 +02:00
|
|
|
ctx->frame_data_array = av_calloc(ctx->frame_data_array_nb, sizeof(*ctx->frame_data_array));
|
|
|
|
if (!ctx->frame_data_array)
|
|
|
|
return AVERROR(ENOMEM);
|
|
|
|
|
2023-06-16 20:23:26 +02:00
|
|
|
ctx->timestamp_list = av_fifo_alloc2(ctx->nb_surfaces, sizeof(int64_t), 0);
|
|
|
|
if (!ctx->timestamp_list)
|
2016-05-20 18:13:20 +02:00
|
|
|
return AVERROR(ENOMEM);
|
2017-04-25 23:57:56 +02:00
|
|
|
|
2022-01-06 17:59:49 +02:00
|
|
|
ctx->unused_surface_queue = av_fifo_alloc2(ctx->nb_surfaces, sizeof(NvencSurface*), 0);
|
2017-04-25 23:57:56 +02:00
|
|
|
if (!ctx->unused_surface_queue)
|
|
|
|
return AVERROR(ENOMEM);
|
|
|
|
|
2022-01-06 17:59:49 +02:00
|
|
|
ctx->output_surface_queue = av_fifo_alloc2(ctx->nb_surfaces, sizeof(NvencSurface*), 0);
|
2016-05-20 18:13:20 +02:00
|
|
|
if (!ctx->output_surface_queue)
|
|
|
|
return AVERROR(ENOMEM);
|
2022-01-06 17:59:49 +02:00
|
|
|
ctx->output_surface_ready_queue = av_fifo_alloc2(ctx->nb_surfaces, sizeof(NvencSurface*), 0);
|
2016-05-20 18:13:20 +02:00
|
|
|
if (!ctx->output_surface_ready_queue)
|
|
|
|
return AVERROR(ENOMEM);
|
|
|
|
|
2017-11-11 17:13:24 +02:00
|
|
|
res = nvenc_push_context(avctx);
|
|
|
|
if (res < 0)
|
|
|
|
return res;
|
2017-05-31 04:03:14 +02:00
|
|
|
|
2016-05-29 12:07:34 +02:00
|
|
|
for (i = 0; i < ctx->nb_surfaces; i++) {
|
2016-05-25 18:57:11 +02:00
|
|
|
if ((res = nvenc_alloc_surface(avctx, i)) < 0)
|
2017-11-15 19:33:31 +02:00
|
|
|
goto fail;
|
2017-05-31 04:03:14 +02:00
|
|
|
}
|
|
|
|
|
2017-11-15 19:33:31 +02:00
|
|
|
fail:
|
|
|
|
res2 = nvenc_pop_context(avctx);
|
|
|
|
if (res2 < 0)
|
|
|
|
return res2;
|
2014-11-30 01:04:37 +02:00
|
|
|
|
2017-11-15 19:33:31 +02:00
|
|
|
return res;
|
2016-05-20 16:49:24 +02:00
|
|
|
}
|
2014-11-30 01:04:37 +02:00
|
|
|
|
2016-05-20 16:49:24 +02:00
|
|
|
static av_cold int nvenc_setup_extradata(AVCodecContext *avctx)
|
|
|
|
{
|
|
|
|
NvencContext *ctx = avctx->priv_data;
|
|
|
|
NvencDynLoadFunctions *dl_fn = &ctx->nvenc_dload_funcs;
|
|
|
|
NV_ENCODE_API_FUNCTION_LIST *p_nvenc = &dl_fn->nvenc_funcs;
|
2014-11-30 01:04:37 +02:00
|
|
|
|
2016-05-20 16:49:24 +02:00
|
|
|
NVENCSTATUS nv_status;
|
|
|
|
uint32_t outSize = 0;
|
2022-11-15 02:32:56 +02:00
|
|
|
char tmpHeader[NV_MAX_SEQ_HDR_LEN];
|
|
|
|
|
2016-05-20 16:49:24 +02:00
|
|
|
NV_ENC_SEQUENCE_PARAM_PAYLOAD payload = { 0 };
|
|
|
|
payload.version = NV_ENC_SEQUENCE_PARAM_PAYLOAD_VER;
|
2014-11-30 01:04:37 +02:00
|
|
|
|
2016-05-20 16:49:24 +02:00
|
|
|
payload.spsppsBuffer = tmpHeader;
|
|
|
|
payload.inBufferSize = sizeof(tmpHeader);
|
|
|
|
payload.outSPSPPSPayloadSize = &outSize;
|
2014-11-30 01:04:37 +02:00
|
|
|
|
2016-05-20 16:49:24 +02:00
|
|
|
nv_status = p_nvenc->nvEncGetSequenceParams(ctx->nvencoder, &payload);
|
|
|
|
if (nv_status != NV_ENC_SUCCESS) {
|
2016-05-20 17:37:00 +02:00
|
|
|
return nvenc_print_error(avctx, nv_status, "GetSequenceParams failed");
|
2016-05-20 16:49:24 +02:00
|
|
|
}
|
2014-11-30 01:04:37 +02:00
|
|
|
|
2016-05-20 16:49:24 +02:00
|
|
|
avctx->extradata_size = outSize;
|
|
|
|
avctx->extradata = av_mallocz(outSize + AV_INPUT_BUFFER_PADDING_SIZE);
|
2014-11-30 01:04:37 +02:00
|
|
|
|
2016-05-20 16:49:24 +02:00
|
|
|
if (!avctx->extradata) {
|
|
|
|
return AVERROR(ENOMEM);
|
|
|
|
}
|
2014-11-30 01:04:37 +02:00
|
|
|
|
2016-05-20 16:49:24 +02:00
|
|
|
memcpy(avctx->extradata, tmpHeader, outSize);
|
2014-11-30 01:04:37 +02:00
|
|
|
|
2016-05-20 16:49:24 +02:00
|
|
|
return 0;
|
|
|
|
}
|
2014-11-30 01:04:37 +02:00
|
|
|
|
2016-05-25 18:57:11 +02:00
|
|
|
av_cold int ff_nvenc_encode_close(AVCodecContext *avctx)
|
2016-05-20 16:49:24 +02:00
|
|
|
{
|
2016-05-25 18:57:11 +02:00
|
|
|
NvencContext *ctx = avctx->priv_data;
|
2016-05-20 16:49:24 +02:00
|
|
|
NvencDynLoadFunctions *dl_fn = &ctx->nvenc_dload_funcs;
|
|
|
|
NV_ENCODE_API_FUNCTION_LIST *p_nvenc = &dl_fn->nvenc_funcs;
|
2017-11-11 17:13:24 +02:00
|
|
|
int i, res;
|
2014-11-30 01:04:37 +02:00
|
|
|
|
2016-05-25 18:57:11 +02:00
|
|
|
/* the encoder has to be flushed before it can be closed */
|
|
|
|
if (ctx->nvencoder) {
|
|
|
|
NV_ENC_PIC_PARAMS params = { .version = NV_ENC_PIC_PARAMS_VER,
|
|
|
|
.encodePicFlags = NV_ENC_PIC_FLAG_EOS };
|
2014-11-30 01:04:37 +02:00
|
|
|
|
2017-11-11 17:13:24 +02:00
|
|
|
res = nvenc_push_context(avctx);
|
|
|
|
if (res < 0)
|
|
|
|
return res;
|
2017-08-30 21:12:23 +02:00
|
|
|
|
2016-05-25 18:57:11 +02:00
|
|
|
p_nvenc->nvEncEncodePicture(ctx->nvencoder, ¶ms);
|
2016-05-20 16:49:24 +02:00
|
|
|
}
|
2015-05-30 16:40:13 +02:00
|
|
|
|
2023-06-16 20:23:26 +02:00
|
|
|
av_fifo_freep2(&ctx->timestamp_list);
|
2022-01-06 17:59:49 +02:00
|
|
|
av_fifo_freep2(&ctx->output_surface_ready_queue);
|
|
|
|
av_fifo_freep2(&ctx->output_surface_queue);
|
|
|
|
av_fifo_freep2(&ctx->unused_surface_queue);
|
2014-11-30 01:04:37 +02:00
|
|
|
|
2023-06-16 21:35:45 +02:00
|
|
|
if (ctx->frame_data_array) {
|
|
|
|
for (i = 0; i < ctx->nb_surfaces; i++)
|
|
|
|
av_buffer_unref(&ctx->frame_data_array[i].frame_opaque_ref);
|
|
|
|
av_freep(&ctx->frame_data_array);
|
|
|
|
}
|
|
|
|
|
2017-11-11 17:51:58 +02:00
|
|
|
if (ctx->surfaces && (avctx->pix_fmt == AV_PIX_FMT_CUDA || avctx->pix_fmt == AV_PIX_FMT_D3D11)) {
|
2016-05-21 00:08:06 +02:00
|
|
|
for (i = 0; i < ctx->nb_registered_frames; i++) {
|
2018-01-26 21:16:53 +02:00
|
|
|
if (ctx->registered_frames[i].mapped)
|
|
|
|
p_nvenc->nvEncUnmapInputResource(ctx->nvencoder, ctx->registered_frames[i].in_map.mappedResource);
|
2016-05-21 00:08:06 +02:00
|
|
|
if (ctx->registered_frames[i].regptr)
|
|
|
|
p_nvenc->nvEncUnregisterResource(ctx->nvencoder, ctx->registered_frames[i].regptr);
|
|
|
|
}
|
|
|
|
ctx->nb_registered_frames = 0;
|
|
|
|
}
|
|
|
|
|
2016-05-25 18:57:11 +02:00
|
|
|
if (ctx->surfaces) {
|
2016-05-29 12:07:34 +02:00
|
|
|
for (i = 0; i < ctx->nb_surfaces; ++i) {
|
2017-11-11 17:51:58 +02:00
|
|
|
if (avctx->pix_fmt != AV_PIX_FMT_CUDA && avctx->pix_fmt != AV_PIX_FMT_D3D11)
|
2016-05-25 18:57:11 +02:00
|
|
|
p_nvenc->nvEncDestroyInputBuffer(ctx->nvencoder, ctx->surfaces[i].input_surface);
|
|
|
|
av_frame_free(&ctx->surfaces[i].in_ref);
|
|
|
|
p_nvenc->nvEncDestroyBitstreamBuffer(ctx->nvencoder, ctx->surfaces[i].output_surface);
|
|
|
|
}
|
2014-11-30 01:04:37 +02:00
|
|
|
}
|
2016-05-20 18:13:20 +02:00
|
|
|
av_freep(&ctx->surfaces);
|
2016-05-29 12:07:34 +02:00
|
|
|
ctx->nb_surfaces = 0;
|
2014-11-30 01:04:37 +02:00
|
|
|
|
2020-06-09 23:31:32 +02:00
|
|
|
av_frame_free(&ctx->frame);
|
|
|
|
|
2021-05-25 12:11:57 +02:00
|
|
|
av_freep(&ctx->sei_data);
|
|
|
|
|
2017-08-30 21:12:23 +02:00
|
|
|
if (ctx->nvencoder) {
|
2016-05-25 18:57:11 +02:00
|
|
|
p_nvenc->nvEncDestroyEncoder(ctx->nvencoder);
|
2014-11-30 01:04:37 +02:00
|
|
|
|
2017-11-11 17:13:24 +02:00
|
|
|
res = nvenc_pop_context(avctx);
|
|
|
|
if (res < 0)
|
|
|
|
return res;
|
2017-05-31 04:03:14 +02:00
|
|
|
}
|
2017-08-30 21:12:23 +02:00
|
|
|
ctx->nvencoder = NULL;
|
2017-05-31 04:03:14 +02:00
|
|
|
|
2016-05-21 00:08:06 +02:00
|
|
|
if (ctx->cu_context_internal)
|
2018-11-11 08:47:28 +02:00
|
|
|
CHECK_CU(dl_fn->cuda_dl->cuCtxDestroy(ctx->cu_context_internal));
|
2016-05-21 00:08:06 +02:00
|
|
|
ctx->cu_context = ctx->cu_context_internal = NULL;
|
2014-11-30 01:04:37 +02:00
|
|
|
|
2017-11-11 17:51:58 +02:00
|
|
|
#if CONFIG_D3D11VA
|
|
|
|
if (ctx->d3d11_device) {
|
|
|
|
ID3D11Device_Release(ctx->d3d11_device);
|
|
|
|
ctx->d3d11_device = NULL;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2016-10-10 12:55:59 +02:00
|
|
|
nvenc_free_functions(&dl_fn->nvenc_dl);
|
|
|
|
cuda_free_functions(&dl_fn->cuda_dl);
|
2016-05-25 18:57:11 +02:00
|
|
|
|
|
|
|
dl_fn->nvenc_device_count = 0;
|
|
|
|
|
|
|
|
av_log(avctx, AV_LOG_VERBOSE, "Nvenc unloaded\n");
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
av_cold int ff_nvenc_encode_init(AVCodecContext *avctx)
|
|
|
|
{
|
2016-05-29 14:23:26 +02:00
|
|
|
NvencContext *ctx = avctx->priv_data;
|
|
|
|
int ret;
|
2016-05-25 18:57:11 +02:00
|
|
|
|
2017-11-11 17:51:58 +02:00
|
|
|
if (avctx->pix_fmt == AV_PIX_FMT_CUDA || avctx->pix_fmt == AV_PIX_FMT_D3D11) {
|
2018-05-07 22:39:20 +02:00
|
|
|
AVHWFramesContext *frames_ctx;
|
|
|
|
if (!avctx->hw_frames_ctx) {
|
2017-11-11 17:51:58 +02:00
|
|
|
av_log(avctx, AV_LOG_ERROR,
|
2018-05-07 22:39:20 +02:00
|
|
|
"hw_frames_ctx must be set when using GPU frames as input\n");
|
2017-11-11 17:51:58 +02:00
|
|
|
return AVERROR(EINVAL);
|
|
|
|
}
|
2018-05-07 22:39:20 +02:00
|
|
|
frames_ctx = (AVHWFramesContext*)avctx->hw_frames_ctx->data;
|
|
|
|
if (frames_ctx->format != avctx->pix_fmt) {
|
|
|
|
av_log(avctx, AV_LOG_ERROR,
|
|
|
|
"hw_frames_ctx must match the GPU frame type\n");
|
|
|
|
return AVERROR(EINVAL);
|
|
|
|
}
|
|
|
|
ctx->data_pix_fmt = frames_ctx->sw_format;
|
2016-05-29 14:23:26 +02:00
|
|
|
} else {
|
|
|
|
ctx->data_pix_fmt = avctx->pix_fmt;
|
|
|
|
}
|
2016-05-25 18:57:11 +02:00
|
|
|
|
2023-10-03 17:31:11 +02:00
|
|
|
if (ctx->rgb_mode == NVENC_RGB_MODE_DISABLED && IS_RGB(ctx->data_pix_fmt)) {
|
|
|
|
av_log(avctx, AV_LOG_ERROR, "Packed RGB input, but RGB support is disabled.\n");
|
|
|
|
return AVERROR(EINVAL);
|
|
|
|
}
|
|
|
|
|
2020-06-09 23:31:32 +02:00
|
|
|
ctx->frame = av_frame_alloc();
|
|
|
|
if (!ctx->frame)
|
|
|
|
return AVERROR(ENOMEM);
|
|
|
|
|
2016-05-29 14:23:26 +02:00
|
|
|
if ((ret = nvenc_load_libraries(avctx)) < 0)
|
|
|
|
return ret;
|
2016-05-25 18:57:11 +02:00
|
|
|
|
2016-05-29 14:23:26 +02:00
|
|
|
if ((ret = nvenc_setup_device(avctx)) < 0)
|
|
|
|
return ret;
|
2016-05-25 18:57:11 +02:00
|
|
|
|
2016-05-29 14:23:26 +02:00
|
|
|
if ((ret = nvenc_setup_encoder(avctx)) < 0)
|
|
|
|
return ret;
|
2016-05-25 18:57:11 +02:00
|
|
|
|
2016-05-29 14:23:26 +02:00
|
|
|
if ((ret = nvenc_setup_surfaces(avctx)) < 0)
|
|
|
|
return ret;
|
2016-05-25 18:57:11 +02:00
|
|
|
|
|
|
|
if (avctx->flags & AV_CODEC_FLAG_GLOBAL_HEADER) {
|
2016-05-29 14:23:26 +02:00
|
|
|
if ((ret = nvenc_setup_extradata(avctx)) < 0)
|
|
|
|
return ret;
|
2016-05-25 18:57:11 +02:00
|
|
|
}
|
2014-11-30 01:04:37 +02:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2016-05-20 17:37:00 +02:00
|
|
|
static NvencSurface *get_free_frame(NvencContext *ctx)
|
2016-05-20 16:49:24 +02:00
|
|
|
{
|
2017-04-25 23:57:56 +02:00
|
|
|
NvencSurface *tmp_surf;
|
2016-05-20 16:49:24 +02:00
|
|
|
|
2022-01-06 17:59:49 +02:00
|
|
|
if (av_fifo_read(ctx->unused_surface_queue, &tmp_surf, 1) < 0)
|
2017-04-25 23:57:56 +02:00
|
|
|
// queue empty
|
|
|
|
return NULL;
|
2016-05-20 16:49:24 +02:00
|
|
|
|
2017-04-25 23:57:56 +02:00
|
|
|
return tmp_surf;
|
2016-05-20 16:49:24 +02:00
|
|
|
}
|
|
|
|
|
2016-09-07 15:49:28 +02:00
|
|
|
static int nvenc_copy_frame(AVCodecContext *avctx, NvencSurface *nv_surface,
|
|
|
|
NV_ENC_LOCK_INPUT_BUFFER *lock_buffer_params, const AVFrame *frame)
|
2016-05-20 16:49:24 +02:00
|
|
|
{
|
2016-09-07 15:49:28 +02:00
|
|
|
int dst_linesize[4] = {
|
|
|
|
lock_buffer_params->pitch,
|
|
|
|
lock_buffer_params->pitch,
|
|
|
|
lock_buffer_params->pitch,
|
|
|
|
lock_buffer_params->pitch
|
|
|
|
};
|
|
|
|
uint8_t *dst_data[4];
|
|
|
|
int ret;
|
2016-08-25 17:18:03 +02:00
|
|
|
|
2016-09-07 15:49:28 +02:00
|
|
|
if (frame->format == AV_PIX_FMT_YUV420P)
|
|
|
|
dst_linesize[1] = dst_linesize[2] >>= 1;
|
2016-08-25 17:18:03 +02:00
|
|
|
|
2016-09-07 15:49:28 +02:00
|
|
|
ret = av_image_fill_pointers(dst_data, frame->format, nv_surface->height,
|
|
|
|
lock_buffer_params->bufferDataPtr, dst_linesize);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
2016-08-25 17:18:03 +02:00
|
|
|
|
2016-09-07 15:49:28 +02:00
|
|
|
if (frame->format == AV_PIX_FMT_YUV420P)
|
|
|
|
FFSWAP(uint8_t*, dst_data[1], dst_data[2]);
|
2016-08-25 17:18:03 +02:00
|
|
|
|
2023-09-07 00:09:10 +02:00
|
|
|
av_image_copy2(dst_data, dst_linesize,
|
|
|
|
frame->data, frame->linesize, frame->format,
|
|
|
|
avctx->width, avctx->height);
|
2016-05-20 16:49:24 +02:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2016-05-21 00:08:06 +02:00
|
|
|
static int nvenc_find_free_reg_resource(AVCodecContext *avctx)
|
|
|
|
{
|
|
|
|
NvencContext *ctx = avctx->priv_data;
|
|
|
|
NvencDynLoadFunctions *dl_fn = &ctx->nvenc_dload_funcs;
|
|
|
|
NV_ENCODE_API_FUNCTION_LIST *p_nvenc = &dl_fn->nvenc_funcs;
|
2018-01-28 13:51:20 +02:00
|
|
|
NVENCSTATUS nv_status;
|
2016-05-21 00:08:06 +02:00
|
|
|
|
2019-04-24 19:00:25 +02:00
|
|
|
int i, first_round;
|
2016-05-21 00:08:06 +02:00
|
|
|
|
|
|
|
if (ctx->nb_registered_frames == FF_ARRAY_ELEMS(ctx->registered_frames)) {
|
2019-04-24 19:00:25 +02:00
|
|
|
for (first_round = 1; first_round >= 0; first_round--) {
|
2019-04-24 22:47:24 +02:00
|
|
|
for (i = 0; i < ctx->nb_registered_frames; i++) {
|
|
|
|
if (!ctx->registered_frames[i].mapped) {
|
|
|
|
if (ctx->registered_frames[i].regptr) {
|
|
|
|
if (first_round)
|
|
|
|
continue;
|
|
|
|
nv_status = p_nvenc->nvEncUnregisterResource(ctx->nvencoder, ctx->registered_frames[i].regptr);
|
|
|
|
if (nv_status != NV_ENC_SUCCESS)
|
|
|
|
return nvenc_print_error(avctx, nv_status, "Failed unregistering unused input resource");
|
|
|
|
ctx->registered_frames[i].ptr = NULL;
|
|
|
|
ctx->registered_frames[i].regptr = NULL;
|
|
|
|
}
|
|
|
|
return i;
|
2016-05-21 00:08:06 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
return ctx->nb_registered_frames++;
|
|
|
|
}
|
|
|
|
|
|
|
|
av_log(avctx, AV_LOG_ERROR, "Too many registered CUDA frames\n");
|
|
|
|
return AVERROR(ENOMEM);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int nvenc_register_frame(AVCodecContext *avctx, const AVFrame *frame)
|
|
|
|
{
|
|
|
|
NvencContext *ctx = avctx->priv_data;
|
|
|
|
NvencDynLoadFunctions *dl_fn = &ctx->nvenc_dload_funcs;
|
|
|
|
NV_ENCODE_API_FUNCTION_LIST *p_nvenc = &dl_fn->nvenc_funcs;
|
|
|
|
|
2018-05-07 22:39:20 +02:00
|
|
|
AVHWFramesContext *frames_ctx = (AVHWFramesContext*)frame->hw_frames_ctx->data;
|
2022-01-10 16:41:50 +02:00
|
|
|
NV_ENC_REGISTER_RESOURCE reg = { 0 };
|
2016-05-21 00:08:06 +02:00
|
|
|
int i, idx, ret;
|
|
|
|
|
|
|
|
for (i = 0; i < ctx->nb_registered_frames; i++) {
|
2017-11-11 17:51:58 +02:00
|
|
|
if (avctx->pix_fmt == AV_PIX_FMT_CUDA && ctx->registered_frames[i].ptr == frame->data[0])
|
|
|
|
return i;
|
|
|
|
else if (avctx->pix_fmt == AV_PIX_FMT_D3D11 && ctx->registered_frames[i].ptr == frame->data[0] && ctx->registered_frames[i].ptr_index == (intptr_t)frame->data[1])
|
2016-05-21 00:08:06 +02:00
|
|
|
return i;
|
|
|
|
}
|
|
|
|
|
|
|
|
idx = nvenc_find_free_reg_resource(avctx);
|
|
|
|
if (idx < 0)
|
|
|
|
return idx;
|
|
|
|
|
|
|
|
reg.version = NV_ENC_REGISTER_RESOURCE_VER;
|
2018-05-07 22:39:20 +02:00
|
|
|
reg.width = frames_ctx->width;
|
|
|
|
reg.height = frames_ctx->height;
|
2016-05-21 00:08:06 +02:00
|
|
|
reg.pitch = frame->linesize[0];
|
|
|
|
reg.resourceToRegister = frame->data[0];
|
|
|
|
|
2017-11-11 17:51:58 +02:00
|
|
|
if (avctx->pix_fmt == AV_PIX_FMT_CUDA) {
|
|
|
|
reg.resourceType = NV_ENC_INPUT_RESOURCE_TYPE_CUDADEVICEPTR;
|
|
|
|
}
|
|
|
|
else if (avctx->pix_fmt == AV_PIX_FMT_D3D11) {
|
|
|
|
reg.resourceType = NV_ENC_INPUT_RESOURCE_TYPE_DIRECTX;
|
|
|
|
reg.subResourceIndex = (intptr_t)frame->data[1];
|
|
|
|
}
|
|
|
|
|
2018-05-07 22:39:20 +02:00
|
|
|
reg.bufferFormat = nvenc_map_buffer_format(frames_ctx->sw_format);
|
2016-11-25 21:11:45 +02:00
|
|
|
if (reg.bufferFormat == NV_ENC_BUFFER_FORMAT_UNDEFINED) {
|
|
|
|
av_log(avctx, AV_LOG_FATAL, "Invalid input pixel format: %s\n",
|
2018-05-07 22:39:20 +02:00
|
|
|
av_get_pix_fmt_name(frames_ctx->sw_format));
|
2016-11-25 21:11:45 +02:00
|
|
|
return AVERROR(EINVAL);
|
|
|
|
}
|
|
|
|
|
2016-05-21 00:08:06 +02:00
|
|
|
ret = p_nvenc->nvEncRegisterResource(ctx->nvencoder, ®);
|
|
|
|
if (ret != NV_ENC_SUCCESS) {
|
|
|
|
nvenc_print_error(avctx, ret, "Error registering an input resource");
|
|
|
|
return AVERROR_UNKNOWN;
|
|
|
|
}
|
|
|
|
|
2017-11-11 17:51:58 +02:00
|
|
|
ctx->registered_frames[idx].ptr = frame->data[0];
|
|
|
|
ctx->registered_frames[idx].ptr_index = reg.subResourceIndex;
|
|
|
|
ctx->registered_frames[idx].regptr = reg.registeredResource;
|
2016-05-21 00:08:06 +02:00
|
|
|
return idx;
|
|
|
|
}
|
|
|
|
|
2016-05-20 16:49:24 +02:00
|
|
|
static int nvenc_upload_frame(AVCodecContext *avctx, const AVFrame *frame,
|
2016-05-20 17:37:00 +02:00
|
|
|
NvencSurface *nvenc_frame)
|
2016-05-20 16:49:24 +02:00
|
|
|
{
|
|
|
|
NvencContext *ctx = avctx->priv_data;
|
|
|
|
NvencDynLoadFunctions *dl_fn = &ctx->nvenc_dload_funcs;
|
|
|
|
NV_ENCODE_API_FUNCTION_LIST *p_nvenc = &dl_fn->nvenc_funcs;
|
|
|
|
|
|
|
|
int res;
|
|
|
|
NVENCSTATUS nv_status;
|
|
|
|
|
2017-11-11 17:51:58 +02:00
|
|
|
if (avctx->pix_fmt == AV_PIX_FMT_CUDA || avctx->pix_fmt == AV_PIX_FMT_D3D11) {
|
2016-05-21 00:08:06 +02:00
|
|
|
int reg_idx = nvenc_register_frame(avctx, frame);
|
|
|
|
if (reg_idx < 0) {
|
2017-11-11 17:51:58 +02:00
|
|
|
av_log(avctx, AV_LOG_ERROR, "Could not register an input HW frame\n");
|
2016-05-21 00:08:06 +02:00
|
|
|
return reg_idx;
|
|
|
|
}
|
2016-05-20 16:49:24 +02:00
|
|
|
|
2016-05-21 00:08:06 +02:00
|
|
|
res = av_frame_ref(nvenc_frame->in_ref, frame);
|
|
|
|
if (res < 0)
|
|
|
|
return res;
|
2016-05-20 16:49:24 +02:00
|
|
|
|
2018-01-26 21:16:53 +02:00
|
|
|
if (!ctx->registered_frames[reg_idx].mapped) {
|
|
|
|
ctx->registered_frames[reg_idx].in_map.version = NV_ENC_MAP_INPUT_RESOURCE_VER;
|
|
|
|
ctx->registered_frames[reg_idx].in_map.registeredResource = ctx->registered_frames[reg_idx].regptr;
|
|
|
|
nv_status = p_nvenc->nvEncMapInputResource(ctx->nvencoder, &ctx->registered_frames[reg_idx].in_map);
|
|
|
|
if (nv_status != NV_ENC_SUCCESS) {
|
|
|
|
av_frame_unref(nvenc_frame->in_ref);
|
|
|
|
return nvenc_print_error(avctx, nv_status, "Error mapping an input resource");
|
|
|
|
}
|
2016-05-21 00:08:06 +02:00
|
|
|
}
|
2016-05-20 16:49:24 +02:00
|
|
|
|
2018-01-26 21:16:53 +02:00
|
|
|
ctx->registered_frames[reg_idx].mapped += 1;
|
|
|
|
|
2016-05-21 00:08:06 +02:00
|
|
|
nvenc_frame->reg_idx = reg_idx;
|
2018-01-26 21:16:53 +02:00
|
|
|
nvenc_frame->input_surface = ctx->registered_frames[reg_idx].in_map.mappedResource;
|
|
|
|
nvenc_frame->format = ctx->registered_frames[reg_idx].in_map.mappedBufferFmt;
|
2016-09-07 18:15:22 +02:00
|
|
|
nvenc_frame->pitch = frame->linesize[0];
|
2018-01-26 21:16:53 +02:00
|
|
|
|
2016-05-21 00:08:06 +02:00
|
|
|
return 0;
|
|
|
|
} else {
|
|
|
|
NV_ENC_LOCK_INPUT_BUFFER lockBufferParams = { 0 };
|
2016-05-20 16:49:24 +02:00
|
|
|
|
2016-05-21 00:08:06 +02:00
|
|
|
lockBufferParams.version = NV_ENC_LOCK_INPUT_BUFFER_VER;
|
|
|
|
lockBufferParams.inputBuffer = nvenc_frame->input_surface;
|
|
|
|
|
|
|
|
nv_status = p_nvenc->nvEncLockInputBuffer(ctx->nvencoder, &lockBufferParams);
|
|
|
|
if (nv_status != NV_ENC_SUCCESS) {
|
|
|
|
return nvenc_print_error(avctx, nv_status, "Failed locking nvenc input buffer");
|
|
|
|
}
|
|
|
|
|
2016-09-07 18:15:22 +02:00
|
|
|
nvenc_frame->pitch = lockBufferParams.pitch;
|
2016-05-21 00:08:06 +02:00
|
|
|
res = nvenc_copy_frame(avctx, nvenc_frame, &lockBufferParams, frame);
|
|
|
|
|
|
|
|
nv_status = p_nvenc->nvEncUnlockInputBuffer(ctx->nvencoder, nvenc_frame->input_surface);
|
|
|
|
if (nv_status != NV_ENC_SUCCESS) {
|
|
|
|
return nvenc_print_error(avctx, nv_status, "Failed unlocking input buffer!");
|
|
|
|
}
|
|
|
|
|
|
|
|
return res;
|
|
|
|
}
|
2016-05-20 16:49:24 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
static void nvenc_codec_specific_pic_params(AVCodecContext *avctx,
|
2018-03-22 11:30:06 +02:00
|
|
|
NV_ENC_PIC_PARAMS *params,
|
2020-06-15 16:08:40 +02:00
|
|
|
NV_ENC_SEI_PAYLOAD *sei_data,
|
|
|
|
int sei_count)
|
2016-05-20 16:49:24 +02:00
|
|
|
{
|
|
|
|
NvencContext *ctx = avctx->priv_data;
|
|
|
|
|
|
|
|
switch (avctx->codec->id) {
|
|
|
|
case AV_CODEC_ID_H264:
|
2016-05-29 14:50:06 +02:00
|
|
|
params->codecPicParams.h264PicParams.sliceMode =
|
|
|
|
ctx->encode_config.encodeCodecConfig.h264Config.sliceMode;
|
|
|
|
params->codecPicParams.h264PicParams.sliceModeData =
|
|
|
|
ctx->encode_config.encodeCodecConfig.h264Config.sliceModeData;
|
2020-06-15 16:08:40 +02:00
|
|
|
if (sei_count > 0) {
|
2018-03-22 11:30:06 +02:00
|
|
|
params->codecPicParams.h264PicParams.seiPayloadArray = sei_data;
|
2020-06-15 16:08:40 +02:00
|
|
|
params->codecPicParams.h264PicParams.seiPayloadArrayCnt = sei_count;
|
2018-03-22 11:30:06 +02:00
|
|
|
}
|
|
|
|
|
2016-05-20 16:49:24 +02:00
|
|
|
break;
|
2016-05-29 14:50:06 +02:00
|
|
|
case AV_CODEC_ID_HEVC:
|
|
|
|
params->codecPicParams.hevcPicParams.sliceMode =
|
|
|
|
ctx->encode_config.encodeCodecConfig.hevcConfig.sliceMode;
|
|
|
|
params->codecPicParams.hevcPicParams.sliceModeData =
|
|
|
|
ctx->encode_config.encodeCodecConfig.hevcConfig.sliceModeData;
|
2020-06-15 16:08:40 +02:00
|
|
|
if (sei_count > 0) {
|
2018-03-22 11:30:06 +02:00
|
|
|
params->codecPicParams.hevcPicParams.seiPayloadArray = sei_data;
|
2020-06-15 16:08:40 +02:00
|
|
|
params->codecPicParams.hevcPicParams.seiPayloadArrayCnt = sei_count;
|
2018-03-22 11:30:06 +02:00
|
|
|
}
|
|
|
|
|
2016-05-29 14:50:06 +02:00
|
|
|
break;
|
2022-11-05 22:17:37 +02:00
|
|
|
#if CONFIG_AV1_NVENC_ENCODER
|
|
|
|
case AV_CODEC_ID_AV1:
|
|
|
|
params->codecPicParams.av1PicParams.numTileColumns =
|
|
|
|
ctx->encode_config.encodeCodecConfig.av1Config.numTileColumns;
|
|
|
|
params->codecPicParams.av1PicParams.numTileRows =
|
|
|
|
ctx->encode_config.encodeCodecConfig.av1Config.numTileRows;
|
|
|
|
if (sei_count > 0) {
|
|
|
|
params->codecPicParams.av1PicParams.obuPayloadArray = sei_data;
|
|
|
|
params->codecPicParams.av1PicParams.obuPayloadArrayCnt = sei_count;
|
|
|
|
}
|
|
|
|
|
|
|
|
break;
|
|
|
|
#endif
|
2016-05-20 16:49:24 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2023-06-16 20:23:26 +02:00
|
|
|
static inline void timestamp_queue_enqueue(AVFifo *queue, int64_t timestamp)
|
2016-05-29 14:50:06 +02:00
|
|
|
{
|
2023-06-16 20:23:26 +02:00
|
|
|
av_fifo_write(queue, ×tamp, 1);
|
2016-05-29 14:50:06 +02:00
|
|
|
}
|
|
|
|
|
2023-06-16 20:23:26 +02:00
|
|
|
static inline int64_t timestamp_queue_dequeue(AVFifo *queue)
|
2016-05-29 14:50:06 +02:00
|
|
|
{
|
2023-06-16 20:23:26 +02:00
|
|
|
int64_t timestamp = AV_NOPTS_VALUE;
|
2022-01-06 17:59:49 +02:00
|
|
|
// The following call might fail if the queue is empty.
|
2023-06-16 20:23:26 +02:00
|
|
|
av_fifo_read(queue, ×tamp, 1);
|
2022-07-12 11:25:09 +02:00
|
|
|
|
2023-06-16 20:23:26 +02:00
|
|
|
return timestamp;
|
2016-05-29 14:50:06 +02:00
|
|
|
}
|
|
|
|
|
2016-05-29 14:34:38 +02:00
|
|
|
static int nvenc_set_timestamp(AVCodecContext *avctx,
|
|
|
|
NV_ENC_LOCK_BITSTREAM *params,
|
|
|
|
AVPacket *pkt)
|
|
|
|
{
|
|
|
|
NvencContext *ctx = avctx->priv_data;
|
|
|
|
|
|
|
|
pkt->pts = params->outputTimeStamp;
|
|
|
|
|
2022-11-05 22:20:06 +02:00
|
|
|
if (avctx->codec_descriptor->props & AV_CODEC_PROP_REORDER) {
|
2023-05-04 11:50:48 +02:00
|
|
|
FF_DISABLE_DEPRECATION_WARNINGS
|
2023-06-16 20:23:26 +02:00
|
|
|
pkt->dts = timestamp_queue_dequeue(ctx->timestamp_list) -
|
2023-05-04 11:50:48 +02:00
|
|
|
#if FF_API_TICKS_PER_FRAME
|
Revert "avcodec/nvenc: fix b-frame DTS behavior with fractional framerates"
This reverts commit 9a245bdf5d7860b8bc5e5c21a105a075925b719a.
This commit basically broke all samples with fractional framerates,
rather than fixing them.
I at this point do not understand the original issue anymore, and I'm
not sure how this slipped my initial testing.
All my test samples must have happened to have a simple timebase.
The actual dts values pretty much always are just a simple chain of
1,2,3,4,5,... Or maybe slightly bigger steps. Each increase by one means
an advance in time by one unit of the timebase.
So a fractional framerate/timebase is already not an issue.
So with this patch applied, the calculation might end up substracting
huge values (1001 is a common one) from the dts, which would be an
offset of that many frames, not of that many fractions of a second.
This broke at least muxing into mp4, if the sample happened to have a
fractional framerate.
I do not thing the original issue this patch tried to fix existed in the
first place, so it can be reverted without further consequences.
2023-06-15 00:45:44 +02:00
|
|
|
FFMAX(avctx->ticks_per_frame, 1) *
|
2023-05-04 11:50:48 +02:00
|
|
|
#endif
|
Revert "avcodec/nvenc: fix b-frame DTS behavior with fractional framerates"
This reverts commit 9a245bdf5d7860b8bc5e5c21a105a075925b719a.
This commit basically broke all samples with fractional framerates,
rather than fixing them.
I at this point do not understand the original issue anymore, and I'm
not sure how this slipped my initial testing.
All my test samples must have happened to have a simple timebase.
The actual dts values pretty much always are just a simple chain of
1,2,3,4,5,... Or maybe slightly bigger steps. Each increase by one means
an advance in time by one unit of the timebase.
So a fractional framerate/timebase is already not an issue.
So with this patch applied, the calculation might end up substracting
huge values (1001 is a common one) from the dts, which would be an
offset of that many frames, not of that many fractions of a second.
This broke at least muxing into mp4, if the sample happened to have a
fractional framerate.
I do not thing the original issue this patch tried to fix existed in the
first place, so it can be reverted without further consequences.
2023-06-15 00:45:44 +02:00
|
|
|
FFMAX(ctx->encode_config.frameIntervalP - 1, 0);
|
2023-05-04 11:50:48 +02:00
|
|
|
FF_ENABLE_DEPRECATION_WARNINGS
|
2022-11-05 22:20:06 +02:00
|
|
|
} else {
|
|
|
|
pkt->dts = pkt->pts;
|
|
|
|
}
|
2016-05-29 14:34:38 +02:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2023-06-16 21:35:45 +02:00
|
|
|
static int nvenc_store_frame_data(AVCodecContext *avctx, NV_ENC_PIC_PARAMS *pic_params, const AVFrame *frame)
|
|
|
|
{
|
|
|
|
NvencContext *ctx = avctx->priv_data;
|
|
|
|
int res = 0;
|
|
|
|
|
|
|
|
int idx = ctx->frame_data_array_pos;
|
|
|
|
NvencFrameData *frame_data = &ctx->frame_data_array[idx];
|
|
|
|
|
|
|
|
// in case the encoder got reconfigured, there might be leftovers
|
|
|
|
av_buffer_unref(&frame_data->frame_opaque_ref);
|
|
|
|
|
2023-07-31 11:50:21 +02:00
|
|
|
if (frame->opaque_ref && avctx->flags & AV_CODEC_FLAG_COPY_OPAQUE) {
|
2023-06-16 21:35:45 +02:00
|
|
|
frame_data->frame_opaque_ref = av_buffer_ref(frame->opaque_ref);
|
|
|
|
if (!frame_data->frame_opaque_ref)
|
|
|
|
return AVERROR(ENOMEM);
|
|
|
|
}
|
|
|
|
|
|
|
|
frame_data->duration = frame->duration;
|
|
|
|
frame_data->frame_opaque = frame->opaque;
|
|
|
|
|
|
|
|
ctx->frame_data_array_pos = (ctx->frame_data_array_pos + 1) % ctx->frame_data_array_nb;
|
|
|
|
pic_params->inputDuration = idx;
|
|
|
|
|
|
|
|
return res;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int nvenc_retrieve_frame_data(AVCodecContext *avctx, NV_ENC_LOCK_BITSTREAM *lock_params, AVPacket *pkt)
|
|
|
|
{
|
|
|
|
NvencContext *ctx = avctx->priv_data;
|
|
|
|
int res = 0;
|
|
|
|
|
|
|
|
int idx = lock_params->outputDuration;
|
|
|
|
NvencFrameData *frame_data = &ctx->frame_data_array[idx];
|
|
|
|
|
|
|
|
pkt->duration = frame_data->duration;
|
|
|
|
|
|
|
|
if (avctx->flags & AV_CODEC_FLAG_COPY_OPAQUE) {
|
|
|
|
pkt->opaque = frame_data->frame_opaque;
|
|
|
|
pkt->opaque_ref = frame_data->frame_opaque_ref;
|
|
|
|
frame_data->frame_opaque_ref = NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
av_buffer_unref(&frame_data->frame_opaque_ref);
|
|
|
|
|
|
|
|
return res;
|
|
|
|
}
|
|
|
|
|
2016-05-20 17:37:00 +02:00
|
|
|
static int process_output_surface(AVCodecContext *avctx, AVPacket *pkt, NvencSurface *tmpoutsurf)
|
2014-11-30 01:04:37 +02:00
|
|
|
{
|
|
|
|
NvencContext *ctx = avctx->priv_data;
|
|
|
|
NvencDynLoadFunctions *dl_fn = &ctx->nvenc_dload_funcs;
|
|
|
|
NV_ENCODE_API_FUNCTION_LIST *p_nvenc = &dl_fn->nvenc_funcs;
|
|
|
|
|
|
|
|
NV_ENC_LOCK_BITSTREAM lock_params = { 0 };
|
|
|
|
NVENCSTATUS nv_status;
|
|
|
|
int res = 0;
|
|
|
|
|
2016-03-08 01:47:56 +02:00
|
|
|
enum AVPictureType pict_type;
|
|
|
|
|
2014-11-30 01:04:37 +02:00
|
|
|
lock_params.version = NV_ENC_LOCK_BITSTREAM_VER;
|
|
|
|
|
|
|
|
lock_params.doNotWait = 0;
|
|
|
|
lock_params.outputBitstream = tmpoutsurf->output_surface;
|
|
|
|
|
|
|
|
nv_status = p_nvenc->nvEncLockBitstream(ctx->nvencoder, &lock_params);
|
|
|
|
if (nv_status != NV_ENC_SUCCESS) {
|
2016-05-20 17:37:00 +02:00
|
|
|
res = nvenc_print_error(avctx, nv_status, "Failed locking bitstream buffer");
|
2014-11-30 01:04:37 +02:00
|
|
|
goto error;
|
|
|
|
}
|
|
|
|
|
2021-03-13 01:50:01 +02:00
|
|
|
res = ff_get_encode_buffer(avctx, pkt, lock_params.bitstreamSizeInBytes, 0);
|
2019-11-17 02:27:44 +02:00
|
|
|
|
|
|
|
if (res < 0) {
|
2014-11-30 01:04:37 +02:00
|
|
|
p_nvenc->nvEncUnlockBitstream(ctx->nvencoder, tmpoutsurf->output_surface);
|
|
|
|
goto error;
|
|
|
|
}
|
|
|
|
|
|
|
|
memcpy(pkt->data, lock_params.bitstreamBufferPtr, lock_params.bitstreamSizeInBytes);
|
|
|
|
|
|
|
|
nv_status = p_nvenc->nvEncUnlockBitstream(ctx->nvencoder, tmpoutsurf->output_surface);
|
2018-01-28 13:51:20 +02:00
|
|
|
if (nv_status != NV_ENC_SUCCESS) {
|
|
|
|
res = nvenc_print_error(avctx, nv_status, "Failed unlocking bitstream buffer, expect the gates of mordor to open");
|
|
|
|
goto error;
|
|
|
|
}
|
2014-11-30 01:04:37 +02:00
|
|
|
|
2016-05-21 00:08:06 +02:00
|
|
|
|
2017-11-11 17:51:58 +02:00
|
|
|
if (avctx->pix_fmt == AV_PIX_FMT_CUDA || avctx->pix_fmt == AV_PIX_FMT_D3D11) {
|
2018-01-26 21:16:53 +02:00
|
|
|
ctx->registered_frames[tmpoutsurf->reg_idx].mapped -= 1;
|
|
|
|
if (ctx->registered_frames[tmpoutsurf->reg_idx].mapped == 0) {
|
2018-01-28 13:51:20 +02:00
|
|
|
nv_status = p_nvenc->nvEncUnmapInputResource(ctx->nvencoder, ctx->registered_frames[tmpoutsurf->reg_idx].in_map.mappedResource);
|
|
|
|
if (nv_status != NV_ENC_SUCCESS) {
|
|
|
|
res = nvenc_print_error(avctx, nv_status, "Failed unmapping input resource");
|
|
|
|
goto error;
|
|
|
|
}
|
2018-01-26 21:16:53 +02:00
|
|
|
} else if (ctx->registered_frames[tmpoutsurf->reg_idx].mapped < 0) {
|
|
|
|
res = AVERROR_BUG;
|
|
|
|
goto error;
|
|
|
|
}
|
|
|
|
|
2016-05-21 00:08:06 +02:00
|
|
|
av_frame_unref(tmpoutsurf->in_ref);
|
|
|
|
|
|
|
|
tmpoutsurf->input_surface = NULL;
|
|
|
|
}
|
|
|
|
|
2014-11-30 01:04:37 +02:00
|
|
|
switch (lock_params.pictureType) {
|
|
|
|
case NV_ENC_PIC_TYPE_IDR:
|
|
|
|
pkt->flags |= AV_PKT_FLAG_KEY;
|
|
|
|
case NV_ENC_PIC_TYPE_I:
|
2016-03-08 01:47:56 +02:00
|
|
|
pict_type = AV_PICTURE_TYPE_I;
|
2014-11-30 01:04:37 +02:00
|
|
|
break;
|
|
|
|
case NV_ENC_PIC_TYPE_P:
|
2016-03-08 01:47:56 +02:00
|
|
|
pict_type = AV_PICTURE_TYPE_P;
|
2014-11-30 01:04:37 +02:00
|
|
|
break;
|
|
|
|
case NV_ENC_PIC_TYPE_B:
|
2016-03-08 01:47:56 +02:00
|
|
|
pict_type = AV_PICTURE_TYPE_B;
|
2014-11-30 01:04:37 +02:00
|
|
|
break;
|
|
|
|
case NV_ENC_PIC_TYPE_BI:
|
2016-03-08 01:47:56 +02:00
|
|
|
pict_type = AV_PICTURE_TYPE_BI;
|
2014-11-30 01:04:37 +02:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
av_log(avctx, AV_LOG_ERROR, "Unknown picture type encountered, expect the output to be broken.\n");
|
|
|
|
av_log(avctx, AV_LOG_ERROR, "Please report this error and include as much information on how to reproduce it as possible.\n");
|
|
|
|
res = AVERROR_EXTERNAL;
|
|
|
|
goto error;
|
2016-03-08 01:47:56 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
ff_side_data_set_encoder_stats(pkt,
|
|
|
|
(lock_params.frameAvgQP - 1) * FF_QP2LAMBDA, NULL, 0, pict_type);
|
2014-11-30 01:04:37 +02:00
|
|
|
|
2016-05-29 14:34:38 +02:00
|
|
|
res = nvenc_set_timestamp(avctx, &lock_params, pkt);
|
|
|
|
if (res < 0)
|
|
|
|
goto error2;
|
2014-11-30 01:04:37 +02:00
|
|
|
|
2023-06-16 21:35:45 +02:00
|
|
|
res = nvenc_retrieve_frame_data(avctx, &lock_params, pkt);
|
|
|
|
if (res < 0)
|
|
|
|
goto error2;
|
|
|
|
|
2014-11-30 01:04:37 +02:00
|
|
|
return 0;
|
|
|
|
|
|
|
|
error:
|
2023-06-16 20:23:26 +02:00
|
|
|
timestamp_queue_dequeue(ctx->timestamp_list);
|
2014-11-30 01:04:37 +02:00
|
|
|
|
2016-05-29 14:34:38 +02:00
|
|
|
error2:
|
2014-11-30 01:04:37 +02:00
|
|
|
return res;
|
|
|
|
}
|
|
|
|
|
2016-05-29 14:50:06 +02:00
|
|
|
static int output_ready(AVCodecContext *avctx, int flush)
|
2016-05-20 18:13:20 +02:00
|
|
|
{
|
2016-05-29 14:50:06 +02:00
|
|
|
NvencContext *ctx = avctx->priv_data;
|
2016-05-20 18:13:20 +02:00
|
|
|
int nb_ready, nb_pending;
|
|
|
|
|
2022-01-06 17:59:49 +02:00
|
|
|
nb_ready = av_fifo_can_read(ctx->output_surface_ready_queue);
|
|
|
|
nb_pending = av_fifo_can_read(ctx->output_surface_queue);
|
2016-05-29 14:50:06 +02:00
|
|
|
if (flush)
|
|
|
|
return nb_ready > 0;
|
|
|
|
return (nb_ready > 0) && (nb_ready + nb_pending >= ctx->async_depth);
|
2016-05-20 18:13:20 +02:00
|
|
|
}
|
|
|
|
|
2021-06-04 18:40:17 +02:00
|
|
|
static int prepare_sei_data_array(AVCodecContext *avctx, const AVFrame *frame)
|
|
|
|
{
|
|
|
|
NvencContext *ctx = avctx->priv_data;
|
|
|
|
int sei_count = 0;
|
|
|
|
int i, res;
|
|
|
|
|
|
|
|
if (ctx->a53_cc && av_frame_get_side_data(frame, AV_FRAME_DATA_A53_CC)) {
|
|
|
|
void *a53_data = NULL;
|
|
|
|
size_t a53_size = 0;
|
|
|
|
|
|
|
|
if (ff_alloc_a53_sei(frame, 0, &a53_data, &a53_size) < 0) {
|
|
|
|
av_log(ctx, AV_LOG_ERROR, "Not enough memory for closed captions, skipping\n");
|
|
|
|
}
|
|
|
|
|
|
|
|
if (a53_data) {
|
|
|
|
void *tmp = av_fast_realloc(ctx->sei_data,
|
|
|
|
&ctx->sei_data_size,
|
|
|
|
(sei_count + 1) * sizeof(*ctx->sei_data));
|
|
|
|
if (!tmp) {
|
|
|
|
av_free(a53_data);
|
|
|
|
res = AVERROR(ENOMEM);
|
|
|
|
goto error;
|
|
|
|
} else {
|
|
|
|
ctx->sei_data = tmp;
|
|
|
|
ctx->sei_data[sei_count].payloadSize = (uint32_t)a53_size;
|
|
|
|
ctx->sei_data[sei_count].payload = (uint8_t*)a53_data;
|
2022-11-05 22:18:36 +02:00
|
|
|
|
|
|
|
#if CONFIG_AV1_NVENC_ENCODER
|
|
|
|
if (avctx->codec->id == AV_CODEC_ID_AV1)
|
|
|
|
ctx->sei_data[sei_count].payloadType = AV1_METADATA_TYPE_ITUT_T35;
|
|
|
|
else
|
|
|
|
#endif
|
|
|
|
ctx->sei_data[sei_count].payloadType = SEI_TYPE_USER_DATA_REGISTERED_ITU_T_T35;
|
|
|
|
|
2021-06-04 18:40:17 +02:00
|
|
|
sei_count++;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (ctx->s12m_tc && av_frame_get_side_data(frame, AV_FRAME_DATA_S12M_TIMECODE)) {
|
|
|
|
void *tc_data = NULL;
|
|
|
|
size_t tc_size = 0;
|
|
|
|
|
|
|
|
if (ff_alloc_timecode_sei(frame, avctx->framerate, 0, &tc_data, &tc_size) < 0) {
|
|
|
|
av_log(ctx, AV_LOG_ERROR, "Not enough memory for timecode sei, skipping\n");
|
|
|
|
}
|
|
|
|
|
|
|
|
if (tc_data) {
|
|
|
|
void *tmp = av_fast_realloc(ctx->sei_data,
|
|
|
|
&ctx->sei_data_size,
|
|
|
|
(sei_count + 1) * sizeof(*ctx->sei_data));
|
|
|
|
if (!tmp) {
|
|
|
|
av_free(tc_data);
|
|
|
|
res = AVERROR(ENOMEM);
|
|
|
|
goto error;
|
|
|
|
} else {
|
|
|
|
ctx->sei_data = tmp;
|
|
|
|
ctx->sei_data[sei_count].payloadSize = (uint32_t)tc_size;
|
|
|
|
ctx->sei_data[sei_count].payload = (uint8_t*)tc_data;
|
2022-11-05 22:18:36 +02:00
|
|
|
|
|
|
|
#if CONFIG_AV1_NVENC_ENCODER
|
|
|
|
if (avctx->codec->id == AV_CODEC_ID_AV1)
|
|
|
|
ctx->sei_data[sei_count].payloadType = AV1_METADATA_TYPE_TIMECODE;
|
|
|
|
else
|
|
|
|
#endif
|
|
|
|
ctx->sei_data[sei_count].payloadType = SEI_TYPE_TIME_CODE;
|
|
|
|
|
2021-06-04 18:40:17 +02:00
|
|
|
sei_count++;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2021-12-24 06:32:47 +02:00
|
|
|
if (!ctx->udu_sei)
|
|
|
|
return sei_count;
|
|
|
|
|
2021-06-04 18:40:17 +02:00
|
|
|
for (i = 0; i < frame->nb_side_data; i++) {
|
|
|
|
AVFrameSideData *side_data = frame->side_data[i];
|
|
|
|
void *tmp;
|
|
|
|
|
|
|
|
if (side_data->type != AV_FRAME_DATA_SEI_UNREGISTERED)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
tmp = av_fast_realloc(ctx->sei_data,
|
|
|
|
&ctx->sei_data_size,
|
|
|
|
(sei_count + 1) * sizeof(*ctx->sei_data));
|
|
|
|
if (!tmp) {
|
|
|
|
res = AVERROR(ENOMEM);
|
|
|
|
goto error;
|
|
|
|
} else {
|
|
|
|
ctx->sei_data = tmp;
|
|
|
|
ctx->sei_data[sei_count].payloadSize = side_data->size;
|
|
|
|
ctx->sei_data[sei_count].payloadType = SEI_TYPE_USER_DATA_UNREGISTERED;
|
|
|
|
ctx->sei_data[sei_count].payload = av_memdup(side_data->data, side_data->size);
|
|
|
|
|
|
|
|
if (!ctx->sei_data[sei_count].payload) {
|
|
|
|
res = AVERROR(ENOMEM);
|
|
|
|
goto error;
|
|
|
|
}
|
|
|
|
|
|
|
|
sei_count++;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return sei_count;
|
|
|
|
|
|
|
|
error:
|
|
|
|
for (i = 0; i < sei_count; i++)
|
|
|
|
av_freep(&(ctx->sei_data[i].payload));
|
|
|
|
|
|
|
|
return res;
|
|
|
|
}
|
|
|
|
|
2018-05-03 18:57:40 +02:00
|
|
|
static void reconfig_encoder(AVCodecContext *avctx, const AVFrame *frame)
|
2017-02-12 20:53:58 +02:00
|
|
|
{
|
|
|
|
NvencContext *ctx = avctx->priv_data;
|
|
|
|
NV_ENCODE_API_FUNCTION_LIST *p_nvenc = &ctx->nvenc_dload_funcs.nvenc_funcs;
|
|
|
|
NVENCSTATUS ret;
|
|
|
|
|
|
|
|
NV_ENC_RECONFIGURE_PARAMS params = { 0 };
|
|
|
|
int needs_reconfig = 0;
|
|
|
|
int needs_encode_config = 0;
|
2018-05-03 02:15:52 +02:00
|
|
|
int reconfig_bitrate = 0, reconfig_dar = 0;
|
2017-02-12 20:53:58 +02:00
|
|
|
int dw, dh;
|
|
|
|
|
|
|
|
params.version = NV_ENC_RECONFIGURE_PARAMS_VER;
|
|
|
|
params.reInitEncodeParams = ctx->init_encode_params;
|
|
|
|
|
|
|
|
compute_dar(avctx, &dw, &dh);
|
|
|
|
if (dw != ctx->init_encode_params.darWidth || dh != ctx->init_encode_params.darHeight) {
|
|
|
|
av_log(avctx, AV_LOG_VERBOSE,
|
|
|
|
"aspect ratio change (DAR): %d:%d -> %d:%d\n",
|
|
|
|
ctx->init_encode_params.darWidth,
|
|
|
|
ctx->init_encode_params.darHeight, dw, dh);
|
|
|
|
|
|
|
|
params.reInitEncodeParams.darHeight = dh;
|
|
|
|
params.reInitEncodeParams.darWidth = dw;
|
|
|
|
|
|
|
|
needs_reconfig = 1;
|
2018-05-03 02:15:52 +02:00
|
|
|
reconfig_dar = 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (ctx->rc != NV_ENC_PARAMS_RC_CONSTQP && ctx->support_dyn_bitrate) {
|
|
|
|
if (avctx->bit_rate > 0 && params.reInitEncodeParams.encodeConfig->rcParams.averageBitRate != avctx->bit_rate) {
|
|
|
|
av_log(avctx, AV_LOG_VERBOSE,
|
|
|
|
"avg bitrate change: %d -> %d\n",
|
|
|
|
params.reInitEncodeParams.encodeConfig->rcParams.averageBitRate,
|
|
|
|
(uint32_t)avctx->bit_rate);
|
|
|
|
|
|
|
|
params.reInitEncodeParams.encodeConfig->rcParams.averageBitRate = avctx->bit_rate;
|
|
|
|
reconfig_bitrate = 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (avctx->rc_max_rate > 0 && ctx->encode_config.rcParams.maxBitRate != avctx->rc_max_rate) {
|
|
|
|
av_log(avctx, AV_LOG_VERBOSE,
|
|
|
|
"max bitrate change: %d -> %d\n",
|
|
|
|
params.reInitEncodeParams.encodeConfig->rcParams.maxBitRate,
|
|
|
|
(uint32_t)avctx->rc_max_rate);
|
|
|
|
|
|
|
|
params.reInitEncodeParams.encodeConfig->rcParams.maxBitRate = avctx->rc_max_rate;
|
|
|
|
reconfig_bitrate = 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (avctx->rc_buffer_size > 0 && ctx->encode_config.rcParams.vbvBufferSize != avctx->rc_buffer_size) {
|
|
|
|
av_log(avctx, AV_LOG_VERBOSE,
|
|
|
|
"vbv buffer size change: %d -> %d\n",
|
|
|
|
params.reInitEncodeParams.encodeConfig->rcParams.vbvBufferSize,
|
|
|
|
avctx->rc_buffer_size);
|
|
|
|
|
|
|
|
params.reInitEncodeParams.encodeConfig->rcParams.vbvBufferSize = avctx->rc_buffer_size;
|
|
|
|
reconfig_bitrate = 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (reconfig_bitrate) {
|
|
|
|
params.resetEncoder = 1;
|
|
|
|
params.forceIDR = 1;
|
|
|
|
|
|
|
|
needs_encode_config = 1;
|
|
|
|
needs_reconfig = 1;
|
|
|
|
}
|
2017-02-12 20:53:58 +02:00
|
|
|
}
|
|
|
|
|
|
|
|
if (!needs_encode_config)
|
|
|
|
params.reInitEncodeParams.encodeConfig = NULL;
|
|
|
|
|
|
|
|
if (needs_reconfig) {
|
|
|
|
ret = p_nvenc->nvEncReconfigureEncoder(ctx->nvencoder, ¶ms);
|
|
|
|
if (ret != NV_ENC_SUCCESS) {
|
|
|
|
nvenc_print_error(avctx, ret, "failed to reconfigure nvenc");
|
|
|
|
} else {
|
2018-05-03 02:15:52 +02:00
|
|
|
if (reconfig_dar) {
|
|
|
|
ctx->init_encode_params.darHeight = dh;
|
|
|
|
ctx->init_encode_params.darWidth = dw;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (reconfig_bitrate) {
|
|
|
|
ctx->encode_config.rcParams.averageBitRate = params.reInitEncodeParams.encodeConfig->rcParams.averageBitRate;
|
|
|
|
ctx->encode_config.rcParams.maxBitRate = params.reInitEncodeParams.encodeConfig->rcParams.maxBitRate;
|
|
|
|
ctx->encode_config.rcParams.vbvBufferSize = params.reInitEncodeParams.encodeConfig->rcParams.vbvBufferSize;
|
|
|
|
}
|
|
|
|
|
2017-02-12 20:53:58 +02:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2020-06-09 23:31:32 +02:00
|
|
|
static int nvenc_send_frame(AVCodecContext *avctx, const AVFrame *frame)
|
2014-11-30 01:04:37 +02:00
|
|
|
{
|
|
|
|
NVENCSTATUS nv_status;
|
2017-09-02 19:42:13 +02:00
|
|
|
NvencSurface *tmp_out_surf, *in_surf;
|
2017-11-11 17:13:24 +02:00
|
|
|
int res, res2;
|
2020-06-15 16:08:40 +02:00
|
|
|
int sei_count = 0;
|
|
|
|
int i;
|
2014-11-30 01:04:37 +02:00
|
|
|
|
|
|
|
NvencContext *ctx = avctx->priv_data;
|
|
|
|
NvencDynLoadFunctions *dl_fn = &ctx->nvenc_dload_funcs;
|
|
|
|
NV_ENCODE_API_FUNCTION_LIST *p_nvenc = &dl_fn->nvenc_funcs;
|
|
|
|
|
|
|
|
NV_ENC_PIC_PARAMS pic_params = { 0 };
|
|
|
|
pic_params.version = NV_ENC_PIC_PARAMS_VER;
|
|
|
|
|
2017-11-11 17:51:58 +02:00
|
|
|
if ((!ctx->cu_context && !ctx->d3d11_device) || !ctx->nvencoder)
|
2017-09-02 19:30:21 +02:00
|
|
|
return AVERROR(EINVAL);
|
|
|
|
|
2020-06-09 23:31:32 +02:00
|
|
|
if (frame && frame->buf[0]) {
|
2017-09-02 19:42:13 +02:00
|
|
|
in_surf = get_free_frame(ctx);
|
|
|
|
if (!in_surf)
|
2017-09-02 19:30:21 +02:00
|
|
|
return AVERROR(EAGAIN);
|
2014-11-30 01:04:37 +02:00
|
|
|
|
2017-11-11 17:13:24 +02:00
|
|
|
res = nvenc_push_context(avctx);
|
|
|
|
if (res < 0)
|
|
|
|
return res;
|
2017-02-13 23:59:46 +02:00
|
|
|
|
2018-05-03 18:57:40 +02:00
|
|
|
reconfig_encoder(avctx, frame);
|
|
|
|
|
2017-09-02 19:42:13 +02:00
|
|
|
res = nvenc_upload_frame(avctx, frame, in_surf);
|
2017-02-13 23:59:46 +02:00
|
|
|
|
2017-11-11 17:13:24 +02:00
|
|
|
res2 = nvenc_pop_context(avctx);
|
|
|
|
if (res2 < 0)
|
|
|
|
return res2;
|
2017-02-13 23:59:46 +02:00
|
|
|
|
2017-09-02 19:30:21 +02:00
|
|
|
if (res)
|
2016-05-20 16:49:24 +02:00
|
|
|
return res;
|
2014-11-30 01:04:37 +02:00
|
|
|
|
2017-09-02 19:42:13 +02:00
|
|
|
pic_params.inputBuffer = in_surf->input_surface;
|
|
|
|
pic_params.bufferFmt = in_surf->format;
|
|
|
|
pic_params.inputWidth = in_surf->width;
|
|
|
|
pic_params.inputHeight = in_surf->height;
|
|
|
|
pic_params.inputPitch = in_surf->pitch;
|
|
|
|
pic_params.outputBitstream = in_surf->output_surface;
|
2014-11-30 01:04:37 +02:00
|
|
|
|
2015-06-29 21:59:37 +02:00
|
|
|
if (avctx->flags & AV_CODEC_FLAG_INTERLACED_DCT) {
|
2023-04-11 20:02:14 +02:00
|
|
|
if (frame->flags & AV_FRAME_FLAG_TOP_FIELD_FIRST)
|
2014-11-30 01:04:37 +02:00
|
|
|
pic_params.pictureStruct = NV_ENC_PIC_STRUCT_FIELD_TOP_BOTTOM;
|
2016-05-29 14:50:06 +02:00
|
|
|
else
|
2014-11-30 01:04:37 +02:00
|
|
|
pic_params.pictureStruct = NV_ENC_PIC_STRUCT_FIELD_BOTTOM_TOP;
|
|
|
|
} else {
|
|
|
|
pic_params.pictureStruct = NV_ENC_PIC_STRUCT_FRAME;
|
|
|
|
}
|
|
|
|
|
2016-10-12 20:51:43 +02:00
|
|
|
if (ctx->forced_idr >= 0 && frame->pict_type == AV_PICTURE_TYPE_I) {
|
|
|
|
pic_params.encodePicFlags =
|
|
|
|
ctx->forced_idr ? NV_ENC_PIC_FLAG_FORCEIDR : NV_ENC_PIC_FLAG_FORCEINTRA;
|
|
|
|
} else {
|
|
|
|
pic_params.encodePicFlags = 0;
|
|
|
|
}
|
|
|
|
|
2024-04-01 00:43:23 +02:00
|
|
|
pic_params.frameIdx = ctx->frame_idx_counter++;
|
2014-11-30 01:04:37 +02:00
|
|
|
pic_params.inputTimeStamp = frame->pts;
|
2016-05-20 16:49:24 +02:00
|
|
|
|
2021-06-06 21:53:53 +02:00
|
|
|
if (ctx->extra_sei) {
|
|
|
|
res = prepare_sei_data_array(avctx, frame);
|
|
|
|
if (res < 0)
|
|
|
|
return res;
|
|
|
|
sei_count = res;
|
|
|
|
}
|
2021-06-04 16:06:38 +02:00
|
|
|
|
2023-06-16 21:35:45 +02:00
|
|
|
res = nvenc_store_frame_data(avctx, &pic_params, frame);
|
|
|
|
if (res < 0)
|
|
|
|
return res;
|
|
|
|
|
2021-05-25 12:11:57 +02:00
|
|
|
nvenc_codec_specific_pic_params(avctx, &pic_params, ctx->sei_data, sei_count);
|
2014-11-30 01:04:37 +02:00
|
|
|
} else {
|
|
|
|
pic_params.encodePicFlags = NV_ENC_PIC_FLAG_EOS;
|
|
|
|
}
|
|
|
|
|
2017-11-11 17:13:24 +02:00
|
|
|
res = nvenc_push_context(avctx);
|
|
|
|
if (res < 0)
|
2023-06-16 20:23:26 +02:00
|
|
|
return res;
|
2017-02-13 23:59:46 +02:00
|
|
|
|
2014-11-30 01:04:37 +02:00
|
|
|
nv_status = p_nvenc->nvEncEncodePicture(ctx->nvencoder, &pic_params);
|
2020-06-15 16:08:40 +02:00
|
|
|
|
2021-05-25 12:11:57 +02:00
|
|
|
for (i = 0; i < sei_count; i++)
|
|
|
|
av_freep(&(ctx->sei_data[i].payload));
|
2017-02-13 23:59:46 +02:00
|
|
|
|
2017-11-11 17:13:24 +02:00
|
|
|
res = nvenc_pop_context(avctx);
|
|
|
|
if (res < 0)
|
2023-06-16 20:23:26 +02:00
|
|
|
return res;
|
2017-02-13 23:59:46 +02:00
|
|
|
|
2016-05-29 14:50:06 +02:00
|
|
|
if (nv_status != NV_ENC_SUCCESS &&
|
2023-06-16 20:23:26 +02:00
|
|
|
nv_status != NV_ENC_ERR_NEED_MORE_INPUT)
|
|
|
|
return nvenc_print_error(avctx, nv_status, "EncodePicture failed!");
|
2014-11-30 01:04:37 +02:00
|
|
|
|
2020-06-09 23:31:32 +02:00
|
|
|
if (frame && frame->buf[0]) {
|
2022-01-06 17:59:49 +02:00
|
|
|
av_fifo_write(ctx->output_surface_queue, &in_surf, 1);
|
2023-06-16 20:23:26 +02:00
|
|
|
|
|
|
|
if (avctx->codec_descriptor->props & AV_CODEC_PROP_REORDER)
|
|
|
|
timestamp_queue_enqueue(ctx->timestamp_list, frame->pts);
|
2016-05-29 14:51:36 +02:00
|
|
|
}
|
2014-11-30 01:04:37 +02:00
|
|
|
|
2016-05-29 14:50:06 +02:00
|
|
|
/* all the pending buffers are now ready for output */
|
|
|
|
if (nv_status == NV_ENC_SUCCESS) {
|
2022-01-06 17:59:49 +02:00
|
|
|
while (av_fifo_read(ctx->output_surface_queue, &tmp_out_surf, 1) >= 0)
|
|
|
|
av_fifo_write(ctx->output_surface_ready_queue, &tmp_out_surf, 1);
|
2014-11-30 01:04:37 +02:00
|
|
|
}
|
|
|
|
|
2017-09-02 19:30:21 +02:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
int ff_nvenc_receive_packet(AVCodecContext *avctx, AVPacket *pkt)
|
|
|
|
{
|
2017-09-02 19:42:13 +02:00
|
|
|
NvencSurface *tmp_out_surf;
|
2017-11-11 17:13:24 +02:00
|
|
|
int res, res2;
|
2017-09-02 19:30:21 +02:00
|
|
|
|
|
|
|
NvencContext *ctx = avctx->priv_data;
|
|
|
|
|
2020-06-09 23:31:32 +02:00
|
|
|
AVFrame *frame = ctx->frame;
|
|
|
|
|
2017-11-11 17:51:58 +02:00
|
|
|
if ((!ctx->cu_context && !ctx->d3d11_device) || !ctx->nvencoder)
|
2017-09-02 19:30:21 +02:00
|
|
|
return AVERROR(EINVAL);
|
|
|
|
|
2020-06-09 23:31:32 +02:00
|
|
|
if (!frame->buf[0]) {
|
|
|
|
res = ff_encode_get_frame(avctx, frame);
|
|
|
|
if (res < 0 && res != AVERROR_EOF)
|
|
|
|
return res;
|
|
|
|
}
|
|
|
|
|
|
|
|
res = nvenc_send_frame(avctx, frame);
|
|
|
|
if (res < 0) {
|
|
|
|
if (res != AVERROR(EAGAIN))
|
|
|
|
return res;
|
|
|
|
} else
|
|
|
|
av_frame_unref(frame);
|
|
|
|
|
|
|
|
if (output_ready(avctx, avctx->internal->draining)) {
|
2022-01-06 17:59:49 +02:00
|
|
|
av_fifo_read(ctx->output_surface_ready_queue, &tmp_out_surf, 1);
|
2014-11-30 01:04:37 +02:00
|
|
|
|
2017-11-11 17:13:24 +02:00
|
|
|
res = nvenc_push_context(avctx);
|
|
|
|
if (res < 0)
|
|
|
|
return res;
|
2017-05-31 04:03:14 +02:00
|
|
|
|
2017-09-02 19:42:13 +02:00
|
|
|
res = process_output_surface(avctx, pkt, tmp_out_surf);
|
2014-11-30 01:04:37 +02:00
|
|
|
|
2017-11-11 17:13:24 +02:00
|
|
|
res2 = nvenc_pop_context(avctx);
|
|
|
|
if (res2 < 0)
|
|
|
|
return res2;
|
2017-05-31 04:03:14 +02:00
|
|
|
|
2014-11-30 01:04:37 +02:00
|
|
|
if (res)
|
|
|
|
return res;
|
|
|
|
|
2022-01-06 17:59:49 +02:00
|
|
|
av_fifo_write(ctx->unused_surface_queue, &tmp_out_surf, 1);
|
2020-06-09 23:31:32 +02:00
|
|
|
} else if (avctx->internal->draining) {
|
2017-09-02 19:30:21 +02:00
|
|
|
return AVERROR_EOF;
|
2014-11-30 01:04:37 +02:00
|
|
|
} else {
|
2017-09-02 19:30:21 +02:00
|
|
|
return AVERROR(EAGAIN);
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2020-06-09 23:31:32 +02:00
|
|
|
av_cold void ff_nvenc_encode_flush(AVCodecContext *avctx)
|
2017-09-02 19:30:21 +02:00
|
|
|
{
|
|
|
|
NvencContext *ctx = avctx->priv_data;
|
2014-11-30 01:04:37 +02:00
|
|
|
|
2020-06-09 23:31:32 +02:00
|
|
|
nvenc_send_frame(avctx, NULL);
|
2023-06-16 20:23:26 +02:00
|
|
|
av_fifo_reset2(ctx->timestamp_list);
|
2019-12-21 01:34:33 +02:00
|
|
|
}
|