2015-07-09 08:34:21 +02:00
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/*
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* Loongson SIMD optimized mpegvideo
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*
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* Copyright (c) 2015 Loongson Technology Corporation Limited
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* Copyright (c) 2015 Zhou Xiaoyong <zhouxiaoyong@loongson.cn>
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* Zhang Shuangshuang <zhangshuangshuang@ict.ac.cn>
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*
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* This file is part of FFmpeg.
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*
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* FFmpeg is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* FFmpeg is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with FFmpeg; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include "mpegvideo_mips.h"
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2016-10-10 10:09:12 +02:00
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#include "libavutil/mips/mmiutils.h"
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2015-07-09 08:34:21 +02:00
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void ff_dct_unquantize_h263_intra_mmi(MpegEncContext *s, int16_t *block,
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int n, int qscale)
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{
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2021-06-01 08:22:09 +02:00
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int64_t level, nCoeffs;
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2016-05-17 07:08:38 +02:00
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double ftmp[6];
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mips_reg addr[1];
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2021-06-01 08:22:09 +02:00
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union mmi_intfloat64 qmul_u, qadd_u;
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2016-10-10 10:09:12 +02:00
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DECLARE_VAR_ALL64;
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2015-07-09 08:34:21 +02:00
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2021-06-01 08:22:09 +02:00
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qmul_u.i = qscale << 1;
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2015-07-15 16:37:58 +02:00
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av_assert2(s->block_last_index[n]>=0 || s->h263_aic);
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2015-07-09 08:34:21 +02:00
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if (!s->h263_aic) {
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if (n<4)
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level = block[0] * s->y_dc_scale;
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else
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level = block[0] * s->c_dc_scale;
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2021-06-01 08:22:09 +02:00
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qadd_u.i = (qscale-1) | 1;
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2015-07-09 08:34:21 +02:00
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} else {
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2021-06-01 08:22:09 +02:00
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qadd_u.i = 0;
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2015-07-09 08:34:21 +02:00
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level = block[0];
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}
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if(s->ac_pred)
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nCoeffs = 63;
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else
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nCoeffs = s->inter_scantable.raster_end[s->block_last_index[n]];
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__asm__ volatile (
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libavcodec/mips: Fix specification of instruction name
1.'xor,or,and' to 'pxor,por,pand'. In the case of operating FPR,
gcc supports both of them, clang only supports the second type.
2.'dsrl,srl' to 'ssrld,ssrlw'. In the case of operating FPR, gcc
supports both of them, clang only supports the second type.
Signed-off-by: Jin Bo <jinbo@loongson.cn>
Reviewed-by: yinshiyou-hf@loongson.cn
Signed-off-by: Michael Niedermayer <michael@niedermayer.cc>
2021-05-28 04:04:39 +02:00
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"pxor %[ftmp0], %[ftmp0], %[ftmp0] \n\t"
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2016-05-17 07:08:38 +02:00
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"packsswh %[qmul], %[qmul], %[qmul] \n\t"
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"packsswh %[qmul], %[qmul], %[qmul] \n\t"
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"packsswh %[qadd], %[qadd], %[qadd] \n\t"
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"packsswh %[qadd], %[qadd], %[qadd] \n\t"
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"psubh %[ftmp0], %[ftmp0], %[qadd] \n\t"
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libavcodec/mips: Fix specification of instruction name
1.'xor,or,and' to 'pxor,por,pand'. In the case of operating FPR,
gcc supports both of them, clang only supports the second type.
2.'dsrl,srl' to 'ssrld,ssrlw'. In the case of operating FPR, gcc
supports both of them, clang only supports the second type.
Signed-off-by: Jin Bo <jinbo@loongson.cn>
Reviewed-by: yinshiyou-hf@loongson.cn
Signed-off-by: Michael Niedermayer <michael@niedermayer.cc>
2021-05-28 04:04:39 +02:00
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"pxor %[ftmp5], %[ftmp5], %[ftmp5] \n\t"
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2016-05-17 07:08:38 +02:00
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".p2align 4 \n\t"
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2016-10-10 10:09:12 +02:00
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2016-05-17 07:08:38 +02:00
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"1: \n\t"
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PTR_ADDU "%[addr0], %[block], %[nCoeffs] \n\t"
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2016-10-10 10:09:12 +02:00
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MMI_LDC1(%[ftmp1], %[addr0], 0x00)
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MMI_LDC1(%[ftmp2], %[addr0], 0x08)
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2016-05-17 07:08:38 +02:00
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"mov.d %[ftmp3], %[ftmp1] \n\t"
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"mov.d %[ftmp4], %[ftmp2] \n\t"
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"pmullh %[ftmp1], %[ftmp1], %[qmul] \n\t"
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"pmullh %[ftmp2], %[ftmp2], %[qmul] \n\t"
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"pcmpgth %[ftmp3], %[ftmp3], %[ftmp5] \n\t"
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"pcmpgth %[ftmp4], %[ftmp4], %[ftmp5] \n\t"
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libavcodec/mips: Fix specification of instruction name
1.'xor,or,and' to 'pxor,por,pand'. In the case of operating FPR,
gcc supports both of them, clang only supports the second type.
2.'dsrl,srl' to 'ssrld,ssrlw'. In the case of operating FPR, gcc
supports both of them, clang only supports the second type.
Signed-off-by: Jin Bo <jinbo@loongson.cn>
Reviewed-by: yinshiyou-hf@loongson.cn
Signed-off-by: Michael Niedermayer <michael@niedermayer.cc>
2021-05-28 04:04:39 +02:00
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"pxor %[ftmp1], %[ftmp1], %[ftmp3] \n\t"
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"pxor %[ftmp2], %[ftmp2], %[ftmp4] \n\t"
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2016-05-17 07:08:38 +02:00
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"paddh %[ftmp1], %[ftmp1], %[ftmp0] \n\t"
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"paddh %[ftmp2], %[ftmp2], %[ftmp0] \n\t"
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libavcodec/mips: Fix specification of instruction name
1.'xor,or,and' to 'pxor,por,pand'. In the case of operating FPR,
gcc supports both of them, clang only supports the second type.
2.'dsrl,srl' to 'ssrld,ssrlw'. In the case of operating FPR, gcc
supports both of them, clang only supports the second type.
Signed-off-by: Jin Bo <jinbo@loongson.cn>
Reviewed-by: yinshiyou-hf@loongson.cn
Signed-off-by: Michael Niedermayer <michael@niedermayer.cc>
2021-05-28 04:04:39 +02:00
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"pxor %[ftmp3], %[ftmp3], %[ftmp1] \n\t"
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"pxor %[ftmp4], %[ftmp4], %[ftmp2] \n\t"
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2016-05-17 07:08:38 +02:00
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"pcmpeqh %[ftmp1], %[ftmp1], %[ftmp0] \n\t"
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"pcmpeqh %[ftmp2], %[ftmp2], %[ftmp0] \n\t"
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"pandn %[ftmp1], %[ftmp1], %[ftmp3] \n\t"
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"pandn %[ftmp2], %[ftmp2], %[ftmp4] \n\t"
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PTR_ADDIU "%[nCoeffs], %[nCoeffs], 0x10 \n\t"
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2016-10-10 10:09:12 +02:00
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MMI_SDC1(%[ftmp1], %[addr0], 0x00)
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MMI_SDC1(%[ftmp2], %[addr0], 0x08)
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2016-05-17 07:08:38 +02:00
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"blez %[nCoeffs], 1b \n\t"
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: [ftmp0]"=&f"(ftmp[0]), [ftmp1]"=&f"(ftmp[1]),
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[ftmp2]"=&f"(ftmp[2]), [ftmp3]"=&f"(ftmp[3]),
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[ftmp4]"=&f"(ftmp[4]), [ftmp5]"=&f"(ftmp[5]),
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2016-10-10 10:09:12 +02:00
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RESTRICT_ASM_ALL64
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2016-05-17 07:08:38 +02:00
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[addr0]"=&r"(addr[0])
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: [block]"r"((mips_reg)(block+nCoeffs)),
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[nCoeffs]"r"((mips_reg)(2*(-nCoeffs))),
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2021-06-01 08:22:09 +02:00
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[qmul]"f"(qmul_u.f), [qadd]"f"(qadd_u.f)
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2016-05-17 07:08:38 +02:00
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: "memory"
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2015-07-09 08:34:21 +02:00
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);
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block[0] = level;
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}
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void ff_dct_unquantize_h263_inter_mmi(MpegEncContext *s, int16_t *block,
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int n, int qscale)
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{
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2021-06-01 08:22:09 +02:00
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int64_t nCoeffs;
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2016-05-17 07:08:38 +02:00
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double ftmp[6];
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mips_reg addr[1];
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2021-06-01 08:22:09 +02:00
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union mmi_intfloat64 qmul_u, qadd_u;
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2016-10-10 10:09:12 +02:00
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DECLARE_VAR_ALL64;
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2015-07-09 08:34:21 +02:00
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2021-06-01 08:22:09 +02:00
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qmul_u.i = qscale << 1;
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qadd_u.i = (qscale - 1) | 1;
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2015-07-15 16:37:58 +02:00
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av_assert2(s->block_last_index[n]>=0 || s->h263_aic);
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2015-07-09 08:34:21 +02:00
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nCoeffs = s->inter_scantable.raster_end[s->block_last_index[n]];
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__asm__ volatile (
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2016-05-17 07:08:38 +02:00
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"packsswh %[qmul], %[qmul], %[qmul] \n\t"
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"packsswh %[qmul], %[qmul], %[qmul] \n\t"
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libavcodec/mips: Fix specification of instruction name
1.'xor,or,and' to 'pxor,por,pand'. In the case of operating FPR,
gcc supports both of them, clang only supports the second type.
2.'dsrl,srl' to 'ssrld,ssrlw'. In the case of operating FPR, gcc
supports both of them, clang only supports the second type.
Signed-off-by: Jin Bo <jinbo@loongson.cn>
Reviewed-by: yinshiyou-hf@loongson.cn
Signed-off-by: Michael Niedermayer <michael@niedermayer.cc>
2021-05-28 04:04:39 +02:00
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"pxor %[ftmp0], %[ftmp0], %[ftmp0] \n\t"
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2016-05-17 07:08:38 +02:00
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"packsswh %[qadd], %[qadd], %[qadd] \n\t"
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"packsswh %[qadd], %[qadd], %[qadd] \n\t"
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"psubh %[ftmp0], %[ftmp0], %[qadd] \n\t"
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libavcodec/mips: Fix specification of instruction name
1.'xor,or,and' to 'pxor,por,pand'. In the case of operating FPR,
gcc supports both of them, clang only supports the second type.
2.'dsrl,srl' to 'ssrld,ssrlw'. In the case of operating FPR, gcc
supports both of them, clang only supports the second type.
Signed-off-by: Jin Bo <jinbo@loongson.cn>
Reviewed-by: yinshiyou-hf@loongson.cn
Signed-off-by: Michael Niedermayer <michael@niedermayer.cc>
2021-05-28 04:04:39 +02:00
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"pxor %[ftmp5], %[ftmp5], %[ftmp5] \n\t"
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2016-05-17 07:08:38 +02:00
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".p2align 4 \n\t"
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"1: \n\t"
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PTR_ADDU "%[addr0], %[block], %[nCoeffs] \n\t"
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2016-10-10 10:09:12 +02:00
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MMI_LDC1(%[ftmp1], %[addr0], 0x00)
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MMI_LDC1(%[ftmp2], %[addr0], 0x08)
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2016-05-17 07:08:38 +02:00
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"mov.d %[ftmp3], %[ftmp1] \n\t"
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"mov.d %[ftmp4], %[ftmp2] \n\t"
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"pmullh %[ftmp1], %[ftmp1], %[qmul] \n\t"
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"pmullh %[ftmp2], %[ftmp2], %[qmul] \n\t"
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"pcmpgth %[ftmp3], %[ftmp3], %[ftmp5] \n\t"
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"pcmpgth %[ftmp4], %[ftmp4], %[ftmp5] \n\t"
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libavcodec/mips: Fix specification of instruction name
1.'xor,or,and' to 'pxor,por,pand'. In the case of operating FPR,
gcc supports both of them, clang only supports the second type.
2.'dsrl,srl' to 'ssrld,ssrlw'. In the case of operating FPR, gcc
supports both of them, clang only supports the second type.
Signed-off-by: Jin Bo <jinbo@loongson.cn>
Reviewed-by: yinshiyou-hf@loongson.cn
Signed-off-by: Michael Niedermayer <michael@niedermayer.cc>
2021-05-28 04:04:39 +02:00
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"pxor %[ftmp1], %[ftmp1], %[ftmp3] \n\t"
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"pxor %[ftmp2], %[ftmp2], %[ftmp4] \n\t"
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2016-05-17 07:08:38 +02:00
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"paddh %[ftmp1], %[ftmp1], %[ftmp0] \n\t"
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"paddh %[ftmp2], %[ftmp2], %[ftmp0] \n\t"
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libavcodec/mips: Fix specification of instruction name
1.'xor,or,and' to 'pxor,por,pand'. In the case of operating FPR,
gcc supports both of them, clang only supports the second type.
2.'dsrl,srl' to 'ssrld,ssrlw'. In the case of operating FPR, gcc
supports both of them, clang only supports the second type.
Signed-off-by: Jin Bo <jinbo@loongson.cn>
Reviewed-by: yinshiyou-hf@loongson.cn
Signed-off-by: Michael Niedermayer <michael@niedermayer.cc>
2021-05-28 04:04:39 +02:00
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"pxor %[ftmp3], %[ftmp3], %[ftmp1] \n\t"
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"pxor %[ftmp4], %[ftmp4], %[ftmp2] \n\t"
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2016-05-17 07:08:38 +02:00
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"pcmpeqh %[ftmp1], %[ftmp1], %[ftmp0] \n\t"
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"pcmpeqh %[ftmp2], %[ftmp2], %[ftmp0] \n\t"
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"pandn %[ftmp1], %[ftmp1], %[ftmp3] \n\t"
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"pandn %[ftmp2], %[ftmp2], %[ftmp4] \n\t"
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PTR_ADDIU "%[nCoeffs], %[nCoeffs], 0x10 \n\t"
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2016-10-10 10:09:12 +02:00
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MMI_SDC1(%[ftmp1], %[addr0], 0x00)
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MMI_SDC1(%[ftmp2], %[addr0], 0x08)
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2016-05-17 07:08:38 +02:00
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"blez %[nCoeffs], 1b \n\t"
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: [ftmp0]"=&f"(ftmp[0]), [ftmp1]"=&f"(ftmp[1]),
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[ftmp2]"=&f"(ftmp[2]), [ftmp3]"=&f"(ftmp[3]),
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[ftmp4]"=&f"(ftmp[4]), [ftmp5]"=&f"(ftmp[5]),
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2016-10-10 10:09:12 +02:00
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RESTRICT_ASM_ALL64
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2016-05-17 07:08:38 +02:00
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[addr0]"=&r"(addr[0])
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: [block]"r"((mips_reg)(block+nCoeffs)),
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[nCoeffs]"r"((mips_reg)(2*(-nCoeffs))),
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2021-06-01 08:22:09 +02:00
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[qmul]"f"(qmul_u.f), [qadd]"f"(qadd_u.f)
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2016-05-17 07:08:38 +02:00
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: "memory"
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2015-07-09 08:34:21 +02:00
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);
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}
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void ff_dct_unquantize_mpeg1_intra_mmi(MpegEncContext *s, int16_t *block,
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int n, int qscale)
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{
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int64_t nCoeffs;
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const uint16_t *quant_matrix;
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int block0;
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2016-05-17 07:08:38 +02:00
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double ftmp[10];
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uint64_t tmp[1];
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mips_reg addr[1];
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2016-10-10 10:09:12 +02:00
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DECLARE_VAR_ALL64;
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DECLARE_VAR_ADDRT;
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2015-07-09 08:34:21 +02:00
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2015-07-15 16:37:58 +02:00
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av_assert2(s->block_last_index[n]>=0);
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2015-07-09 08:34:21 +02:00
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nCoeffs = s->intra_scantable.raster_end[s->block_last_index[n]] + 1;
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if (n<4)
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block0 = block[0] * s->y_dc_scale;
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else
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block0 = block[0] * s->c_dc_scale;
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/* XXX: only mpeg1 */
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quant_matrix = s->intra_matrix;
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__asm__ volatile (
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2016-05-17 07:08:38 +02:00
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"dli %[tmp0], 0x0f \n\t"
|
|
|
|
|
"pcmpeqh %[ftmp0], %[ftmp0], %[ftmp0] \n\t"
|
|
|
|
|
"dmtc1 %[tmp0], %[ftmp4] \n\t"
|
|
|
|
|
"dmtc1 %[qscale], %[ftmp1] \n\t"
|
|
|
|
|
"psrlh %[ftmp0], %[ftmp0], %[ftmp4] \n\t"
|
|
|
|
|
"packsswh %[ftmp1], %[ftmp1], %[ftmp1] \n\t"
|
|
|
|
|
"packsswh %[ftmp1], %[ftmp1], %[ftmp1] \n\t"
|
|
|
|
|
"or %[addr0], %[nCoeffs], $0 \n\t"
|
|
|
|
|
".p2align 4 \n\t"
|
2016-10-10 10:09:12 +02:00
|
|
|
|
2016-05-17 07:08:38 +02:00
|
|
|
"1: \n\t"
|
2016-10-10 10:09:12 +02:00
|
|
|
MMI_LDXC1(%[ftmp2], %[addr0], %[block], 0x00)
|
|
|
|
|
MMI_LDXC1(%[ftmp3], %[addr0], %[block], 0x08)
|
2016-05-17 07:08:38 +02:00
|
|
|
"mov.d %[ftmp4], %[ftmp2] \n\t"
|
|
|
|
|
"mov.d %[ftmp5], %[ftmp3] \n\t"
|
2016-10-10 10:09:12 +02:00
|
|
|
MMI_LDXC1(%[ftmp6], %[addr0], %[quant], 0x00)
|
|
|
|
|
MMI_LDXC1(%[ftmp7], %[addr0], %[quant], 0x08)
|
2016-05-17 07:08:38 +02:00
|
|
|
"pmullh %[ftmp6], %[ftmp6], %[ftmp1] \n\t"
|
|
|
|
|
"pmullh %[ftmp7], %[ftmp7], %[ftmp1] \n\t"
|
libavcodec/mips: Fix specification of instruction name
1.'xor,or,and' to 'pxor,por,pand'. In the case of operating FPR,
gcc supports both of them, clang only supports the second type.
2.'dsrl,srl' to 'ssrld,ssrlw'. In the case of operating FPR, gcc
supports both of them, clang only supports the second type.
Signed-off-by: Jin Bo <jinbo@loongson.cn>
Reviewed-by: yinshiyou-hf@loongson.cn
Signed-off-by: Michael Niedermayer <michael@niedermayer.cc>
2021-05-28 04:04:39 +02:00
|
|
|
"pxor %[ftmp8], %[ftmp8], %[ftmp8] \n\t"
|
|
|
|
|
"pxor %[ftmp9], %[ftmp9], %[ftmp9] \n\t"
|
2016-05-17 07:08:38 +02:00
|
|
|
"pcmpgth %[ftmp8], %[ftmp8], %[ftmp2] \n\t"
|
|
|
|
|
"pcmpgth %[ftmp9], %[ftmp9], %[ftmp3] \n\t"
|
libavcodec/mips: Fix specification of instruction name
1.'xor,or,and' to 'pxor,por,pand'. In the case of operating FPR,
gcc supports both of them, clang only supports the second type.
2.'dsrl,srl' to 'ssrld,ssrlw'. In the case of operating FPR, gcc
supports both of them, clang only supports the second type.
Signed-off-by: Jin Bo <jinbo@loongson.cn>
Reviewed-by: yinshiyou-hf@loongson.cn
Signed-off-by: Michael Niedermayer <michael@niedermayer.cc>
2021-05-28 04:04:39 +02:00
|
|
|
"pxor %[ftmp2], %[ftmp2], %[ftmp8] \n\t"
|
|
|
|
|
"pxor %[ftmp3], %[ftmp3], %[ftmp9] \n\t"
|
2016-05-17 07:08:38 +02:00
|
|
|
"psubh %[ftmp2], %[ftmp2], %[ftmp8] \n\t"
|
|
|
|
|
"psubh %[ftmp3], %[ftmp3], %[ftmp9] \n\t"
|
|
|
|
|
"pmullh %[ftmp2], %[ftmp2], %[ftmp6] \n\t"
|
|
|
|
|
"pmullh %[ftmp3], %[ftmp3], %[ftmp7] \n\t"
|
libavcodec/mips: Fix specification of instruction name
1.'xor,or,and' to 'pxor,por,pand'. In the case of operating FPR,
gcc supports both of them, clang only supports the second type.
2.'dsrl,srl' to 'ssrld,ssrlw'. In the case of operating FPR, gcc
supports both of them, clang only supports the second type.
Signed-off-by: Jin Bo <jinbo@loongson.cn>
Reviewed-by: yinshiyou-hf@loongson.cn
Signed-off-by: Michael Niedermayer <michael@niedermayer.cc>
2021-05-28 04:04:39 +02:00
|
|
|
"pxor %[ftmp6], %[ftmp6], %[ftmp6] \n\t"
|
|
|
|
|
"pxor %[ftmp7], %[ftmp7], %[ftmp7] \n\t"
|
2016-05-17 07:08:38 +02:00
|
|
|
"pcmpeqh %[ftmp6], %[ftmp6], %[ftmp4] \n\t"
|
|
|
|
|
"dli %[tmp0], 0x03 \n\t"
|
|
|
|
|
"pcmpeqh %[ftmp7], %[ftmp7], %[ftmp5] \n\t"
|
|
|
|
|
"dmtc1 %[tmp0], %[ftmp4] \n\t"
|
|
|
|
|
"psrah %[ftmp2], %[ftmp2], %[ftmp4] \n\t"
|
|
|
|
|
"psrah %[ftmp3], %[ftmp3], %[ftmp4] \n\t"
|
|
|
|
|
"psubh %[ftmp2], %[ftmp2], %[ftmp0] \n\t"
|
|
|
|
|
"psubh %[ftmp3], %[ftmp3], %[ftmp0] \n\t"
|
libavcodec/mips: Fix specification of instruction name
1.'xor,or,and' to 'pxor,por,pand'. In the case of operating FPR,
gcc supports both of them, clang only supports the second type.
2.'dsrl,srl' to 'ssrld,ssrlw'. In the case of operating FPR, gcc
supports both of them, clang only supports the second type.
Signed-off-by: Jin Bo <jinbo@loongson.cn>
Reviewed-by: yinshiyou-hf@loongson.cn
Signed-off-by: Michael Niedermayer <michael@niedermayer.cc>
2021-05-28 04:04:39 +02:00
|
|
|
"por %[ftmp2], %[ftmp2], %[ftmp0] \n\t"
|
|
|
|
|
"por %[ftmp3], %[ftmp3], %[ftmp0] \n\t"
|
|
|
|
|
"pxor %[ftmp2], %[ftmp2], %[ftmp8] \n\t"
|
|
|
|
|
"pxor %[ftmp3], %[ftmp3], %[ftmp9] \n\t"
|
2016-05-17 07:08:38 +02:00
|
|
|
"psubh %[ftmp2], %[ftmp2], %[ftmp8] \n\t"
|
|
|
|
|
"psubh %[ftmp3], %[ftmp3], %[ftmp9] \n\t"
|
|
|
|
|
"pandn %[ftmp6], %[ftmp6], %[ftmp2] \n\t"
|
|
|
|
|
"pandn %[ftmp7], %[ftmp7], %[ftmp3] \n\t"
|
2016-10-10 10:09:12 +02:00
|
|
|
MMI_SDXC1(%[ftmp6], %[addr0], %[block], 0x00)
|
|
|
|
|
MMI_SDXC1(%[ftmp7], %[addr0], %[block], 0x08)
|
2016-05-17 07:08:38 +02:00
|
|
|
PTR_ADDIU "%[addr0], %[addr0], 0x10 \n\t"
|
|
|
|
|
"bltz %[addr0], 1b \n\t"
|
|
|
|
|
: [ftmp0]"=&f"(ftmp[0]), [ftmp1]"=&f"(ftmp[1]),
|
|
|
|
|
[ftmp2]"=&f"(ftmp[2]), [ftmp3]"=&f"(ftmp[3]),
|
|
|
|
|
[ftmp4]"=&f"(ftmp[4]), [ftmp5]"=&f"(ftmp[5]),
|
|
|
|
|
[ftmp6]"=&f"(ftmp[6]), [ftmp7]"=&f"(ftmp[7]),
|
|
|
|
|
[ftmp8]"=&f"(ftmp[8]), [ftmp9]"=&f"(ftmp[9]),
|
|
|
|
|
[tmp0]"=&r"(tmp[0]),
|
2016-10-10 10:09:12 +02:00
|
|
|
RESTRICT_ASM_ALL64
|
|
|
|
|
RESTRICT_ASM_ADDRT
|
2016-05-17 07:08:38 +02:00
|
|
|
[addr0]"=&r"(addr[0])
|
|
|
|
|
: [block]"r"((mips_reg)(block+nCoeffs)),
|
|
|
|
|
[quant]"r"((mips_reg)(quant_matrix+nCoeffs)),
|
|
|
|
|
[nCoeffs]"r"((mips_reg)(2*(-nCoeffs))),
|
|
|
|
|
[qscale]"r"(qscale)
|
|
|
|
|
: "memory"
|
2015-07-09 08:34:21 +02:00
|
|
|
);
|
|
|
|
|
|
|
|
|
|
block[0] = block0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void ff_dct_unquantize_mpeg1_inter_mmi(MpegEncContext *s, int16_t *block,
|
|
|
|
|
int n, int qscale)
|
|
|
|
|
{
|
|
|
|
|
int64_t nCoeffs;
|
|
|
|
|
const uint16_t *quant_matrix;
|
2016-05-17 07:08:38 +02:00
|
|
|
double ftmp[10];
|
|
|
|
|
uint64_t tmp[1];
|
|
|
|
|
mips_reg addr[1];
|
2016-10-10 10:09:12 +02:00
|
|
|
DECLARE_VAR_ALL64;
|
|
|
|
|
DECLARE_VAR_ADDRT;
|
2015-07-09 08:34:21 +02:00
|
|
|
|
2015-07-15 16:37:58 +02:00
|
|
|
av_assert2(s->block_last_index[n] >= 0);
|
2015-07-09 08:34:21 +02:00
|
|
|
nCoeffs = s->intra_scantable.raster_end[s->block_last_index[n]] + 1;
|
|
|
|
|
quant_matrix = s->inter_matrix;
|
|
|
|
|
|
|
|
|
|
__asm__ volatile (
|
2016-05-17 07:08:38 +02:00
|
|
|
"dli %[tmp0], 0x0f \n\t"
|
|
|
|
|
"pcmpeqh %[ftmp0], %[ftmp0], %[ftmp0] \n\t"
|
|
|
|
|
"dmtc1 %[tmp0], %[ftmp4] \n\t"
|
|
|
|
|
"dmtc1 %[qscale], %[ftmp1] \n\t"
|
|
|
|
|
"psrlh %[ftmp0], %[ftmp0], %[ftmp4] \n\t"
|
|
|
|
|
"packsswh %[ftmp1], %[ftmp1], %[ftmp1] \n\t"
|
|
|
|
|
"packsswh %[ftmp1], %[ftmp1], %[ftmp1] \n\t"
|
|
|
|
|
"or %[addr0], %[nCoeffs], $0 \n\t"
|
|
|
|
|
".p2align 4 \n\t"
|
2016-10-10 10:09:12 +02:00
|
|
|
|
2016-05-17 07:08:38 +02:00
|
|
|
"1: \n\t"
|
2016-10-10 10:09:12 +02:00
|
|
|
MMI_LDXC1(%[ftmp2], %[addr0], %[block], 0x00)
|
|
|
|
|
MMI_LDXC1(%[ftmp3], %[addr0], %[block], 0x08)
|
2016-05-17 07:08:38 +02:00
|
|
|
"mov.d %[ftmp4], %[ftmp2] \n\t"
|
|
|
|
|
"mov.d %[ftmp5], %[ftmp3] \n\t"
|
2016-10-10 10:09:12 +02:00
|
|
|
MMI_LDXC1(%[ftmp6], %[addr0], %[quant], 0x00)
|
|
|
|
|
MMI_LDXC1(%[ftmp7], %[addr0], %[quant], 0x08)
|
2016-05-17 07:08:38 +02:00
|
|
|
"pmullh %[ftmp6], %[ftmp6], %[ftmp1] \n\t"
|
|
|
|
|
"pmullh %[ftmp7], %[ftmp7], %[ftmp1] \n\t"
|
libavcodec/mips: Fix specification of instruction name
1.'xor,or,and' to 'pxor,por,pand'. In the case of operating FPR,
gcc supports both of them, clang only supports the second type.
2.'dsrl,srl' to 'ssrld,ssrlw'. In the case of operating FPR, gcc
supports both of them, clang only supports the second type.
Signed-off-by: Jin Bo <jinbo@loongson.cn>
Reviewed-by: yinshiyou-hf@loongson.cn
Signed-off-by: Michael Niedermayer <michael@niedermayer.cc>
2021-05-28 04:04:39 +02:00
|
|
|
"pxor %[ftmp8], %[ftmp8], %[ftmp8] \n\t"
|
|
|
|
|
"pxor %[ftmp9], %[ftmp9], %[ftmp9] \n\t"
|
2016-05-17 07:08:38 +02:00
|
|
|
"pcmpgth %[ftmp8], %[ftmp8], %[ftmp2] \n\t"
|
|
|
|
|
"pcmpgth %[ftmp9], %[ftmp9], %[ftmp3] \n\t"
|
libavcodec/mips: Fix specification of instruction name
1.'xor,or,and' to 'pxor,por,pand'. In the case of operating FPR,
gcc supports both of them, clang only supports the second type.
2.'dsrl,srl' to 'ssrld,ssrlw'. In the case of operating FPR, gcc
supports both of them, clang only supports the second type.
Signed-off-by: Jin Bo <jinbo@loongson.cn>
Reviewed-by: yinshiyou-hf@loongson.cn
Signed-off-by: Michael Niedermayer <michael@niedermayer.cc>
2021-05-28 04:04:39 +02:00
|
|
|
"pxor %[ftmp2], %[ftmp2], %[ftmp8] \n\t"
|
|
|
|
|
"pxor %[ftmp3], %[ftmp3], %[ftmp9] \n\t"
|
2016-05-17 07:08:38 +02:00
|
|
|
"psubh %[ftmp2], %[ftmp2], %[ftmp8] \n\t"
|
|
|
|
|
"psubh %[ftmp3], %[ftmp3], %[ftmp9] \n\t"
|
|
|
|
|
"paddh %[ftmp2], %[ftmp2], %[ftmp2] \n\t"
|
|
|
|
|
"paddh %[ftmp3], %[ftmp3], %[ftmp3] \n\t"
|
|
|
|
|
"paddh %[ftmp2], %[ftmp2], %[ftmp0] \n\t"
|
|
|
|
|
"paddh %[ftmp3], %[ftmp3], %[ftmp0] \n\t"
|
|
|
|
|
"pmullh %[ftmp2], %[ftmp2], %[ftmp6] \n\t"
|
|
|
|
|
"pmullh %[ftmp3], %[ftmp3], %[ftmp7] \n\t"
|
libavcodec/mips: Fix specification of instruction name
1.'xor,or,and' to 'pxor,por,pand'. In the case of operating FPR,
gcc supports both of them, clang only supports the second type.
2.'dsrl,srl' to 'ssrld,ssrlw'. In the case of operating FPR, gcc
supports both of them, clang only supports the second type.
Signed-off-by: Jin Bo <jinbo@loongson.cn>
Reviewed-by: yinshiyou-hf@loongson.cn
Signed-off-by: Michael Niedermayer <michael@niedermayer.cc>
2021-05-28 04:04:39 +02:00
|
|
|
"pxor %[ftmp6], %[ftmp6], %[ftmp6] \n\t"
|
|
|
|
|
"pxor %[ftmp7], %[ftmp7], %[ftmp7] \n\t"
|
2016-05-17 07:08:38 +02:00
|
|
|
"pcmpeqh %[ftmp6], %[ftmp6], %[ftmp4] \n\t"
|
|
|
|
|
"dli %[tmp0], 0x04 \n\t"
|
|
|
|
|
"pcmpeqh %[ftmp7], %[ftmp7], %[ftmp5] \n\t"
|
|
|
|
|
"dmtc1 %[tmp0], %[ftmp4] \n\t"
|
|
|
|
|
"psrah %[ftmp2], %[ftmp2], %[ftmp4] \n\t"
|
|
|
|
|
"psrah %[ftmp3], %[ftmp3], %[ftmp4] \n\t"
|
|
|
|
|
"psubh %[ftmp2], %[ftmp2], %[ftmp0] \n\t"
|
|
|
|
|
"psubh %[ftmp3], %[ftmp3], %[ftmp0] \n\t"
|
libavcodec/mips: Fix specification of instruction name
1.'xor,or,and' to 'pxor,por,pand'. In the case of operating FPR,
gcc supports both of them, clang only supports the second type.
2.'dsrl,srl' to 'ssrld,ssrlw'. In the case of operating FPR, gcc
supports both of them, clang only supports the second type.
Signed-off-by: Jin Bo <jinbo@loongson.cn>
Reviewed-by: yinshiyou-hf@loongson.cn
Signed-off-by: Michael Niedermayer <michael@niedermayer.cc>
2021-05-28 04:04:39 +02:00
|
|
|
"por %[ftmp2], %[ftmp2], %[ftmp0] \n\t"
|
|
|
|
|
"por %[ftmp3], %[ftmp3], %[ftmp0] \n\t"
|
|
|
|
|
"pxor %[ftmp2], %[ftmp2], %[ftmp8] \n\t"
|
|
|
|
|
"pxor %[ftmp3], %[ftmp3], %[ftmp9] \n\t"
|
2016-05-17 07:08:38 +02:00
|
|
|
"psubh %[ftmp2], %[ftmp2], %[ftmp8] \n\t"
|
|
|
|
|
"psubh %[ftmp3], %[ftmp3], %[ftmp9] \n\t"
|
|
|
|
|
"pandn %[ftmp6], %[ftmp6], %[ftmp2] \n\t"
|
|
|
|
|
"pandn %[ftmp7], %[ftmp7], %[ftmp3] \n\t"
|
2016-10-10 10:09:12 +02:00
|
|
|
MMI_SDXC1(%[ftmp6], %[addr0], %[block], 0x00)
|
|
|
|
|
MMI_SDXC1(%[ftmp7], %[addr0], %[block], 0x08)
|
2016-05-17 07:08:38 +02:00
|
|
|
PTR_ADDIU "%[addr0], %[addr0], 0x10 \n\t"
|
|
|
|
|
"bltz %[addr0], 1b \n\t"
|
|
|
|
|
: [ftmp0]"=&f"(ftmp[0]), [ftmp1]"=&f"(ftmp[1]),
|
|
|
|
|
[ftmp2]"=&f"(ftmp[2]), [ftmp3]"=&f"(ftmp[3]),
|
|
|
|
|
[ftmp4]"=&f"(ftmp[4]), [ftmp5]"=&f"(ftmp[5]),
|
|
|
|
|
[ftmp6]"=&f"(ftmp[6]), [ftmp7]"=&f"(ftmp[7]),
|
|
|
|
|
[ftmp8]"=&f"(ftmp[8]), [ftmp9]"=&f"(ftmp[9]),
|
|
|
|
|
[tmp0]"=&r"(tmp[0]),
|
2016-10-10 10:09:12 +02:00
|
|
|
RESTRICT_ASM_ALL64
|
|
|
|
|
RESTRICT_ASM_ADDRT
|
2016-05-17 07:08:38 +02:00
|
|
|
[addr0]"=&r"(addr[0])
|
|
|
|
|
: [block]"r"((mips_reg)(block+nCoeffs)),
|
|
|
|
|
[quant]"r"((mips_reg)(quant_matrix+nCoeffs)),
|
|
|
|
|
[nCoeffs]"r"((mips_reg)(2*(-nCoeffs))),
|
|
|
|
|
[qscale]"r"(qscale)
|
|
|
|
|
: "memory"
|
2015-09-02 12:01:00 +02:00
|
|
|
);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void ff_dct_unquantize_mpeg2_intra_mmi(MpegEncContext *s, int16_t *block,
|
|
|
|
|
int n, int qscale)
|
|
|
|
|
{
|
|
|
|
|
uint64_t nCoeffs;
|
|
|
|
|
const uint16_t *quant_matrix;
|
|
|
|
|
int block0;
|
2016-05-17 07:08:38 +02:00
|
|
|
double ftmp[10];
|
|
|
|
|
uint64_t tmp[1];
|
|
|
|
|
mips_reg addr[1];
|
2016-10-10 10:09:12 +02:00
|
|
|
DECLARE_VAR_ALL64;
|
|
|
|
|
DECLARE_VAR_ADDRT;
|
2015-09-02 12:01:00 +02:00
|
|
|
|
|
|
|
|
assert(s->block_last_index[n]>=0);
|
|
|
|
|
|
|
|
|
|
if (s->alternate_scan)
|
|
|
|
|
nCoeffs = 63;
|
|
|
|
|
else
|
|
|
|
|
nCoeffs = s->intra_scantable.raster_end[s->block_last_index[n]];
|
|
|
|
|
|
|
|
|
|
if (n < 4)
|
|
|
|
|
block0 = block[0] * s->y_dc_scale;
|
|
|
|
|
else
|
|
|
|
|
block0 = block[0] * s->c_dc_scale;
|
|
|
|
|
|
|
|
|
|
quant_matrix = s->intra_matrix;
|
|
|
|
|
|
|
|
|
|
__asm__ volatile (
|
2016-05-17 07:08:38 +02:00
|
|
|
"dli %[tmp0], 0x0f \n\t"
|
|
|
|
|
"pcmpeqh %[ftmp0], %[ftmp0], %[ftmp0] \n\t"
|
|
|
|
|
"mtc1 %[tmp0], %[ftmp3] \n\t"
|
|
|
|
|
"mtc1 %[qscale], %[ftmp9] \n\t"
|
|
|
|
|
"psrlh %[ftmp0], %[ftmp0], %[ftmp3] \n\t"
|
|
|
|
|
"packsswh %[ftmp9], %[ftmp9], %[ftmp9] \n\t"
|
|
|
|
|
"packsswh %[ftmp9], %[ftmp9], %[ftmp9] \n\t"
|
|
|
|
|
"or %[addr0], %[nCoeffs], $0 \n\t"
|
|
|
|
|
".p2align 4 \n\t"
|
2016-10-10 10:09:12 +02:00
|
|
|
|
2016-05-17 07:08:38 +02:00
|
|
|
"1: \n\t"
|
2016-10-10 10:09:12 +02:00
|
|
|
MMI_LDXC1(%[ftmp1], %[addr0], %[block], 0x00)
|
|
|
|
|
MMI_LDXC1(%[ftmp2], %[addr0], %[block], 0x08)
|
2016-05-17 07:08:38 +02:00
|
|
|
"mov.d %[ftmp3], %[ftmp1] \n\t"
|
|
|
|
|
"mov.d %[ftmp4], %[ftmp2] \n\t"
|
2016-10-10 10:09:12 +02:00
|
|
|
MMI_LDXC1(%[ftmp5], %[addr0], %[quant], 0x00)
|
|
|
|
|
MMI_LDXC1(%[ftmp6], %[addr0], %[quant], 0x08)
|
2016-05-17 07:08:38 +02:00
|
|
|
"pmullh %[ftmp5], %[ftmp5], %[ftmp9] \n\t"
|
|
|
|
|
"pmullh %[ftmp6], %[ftmp6], %[ftmp9] \n\t"
|
libavcodec/mips: Fix specification of instruction name
1.'xor,or,and' to 'pxor,por,pand'. In the case of operating FPR,
gcc supports both of them, clang only supports the second type.
2.'dsrl,srl' to 'ssrld,ssrlw'. In the case of operating FPR, gcc
supports both of them, clang only supports the second type.
Signed-off-by: Jin Bo <jinbo@loongson.cn>
Reviewed-by: yinshiyou-hf@loongson.cn
Signed-off-by: Michael Niedermayer <michael@niedermayer.cc>
2021-05-28 04:04:39 +02:00
|
|
|
"pxor %[ftmp7], %[ftmp7], %[ftmp7] \n\t"
|
|
|
|
|
"pxor %[ftmp8], %[ftmp8], %[ftmp8] \n\t"
|
2016-05-17 07:08:38 +02:00
|
|
|
"pcmpgth %[ftmp7], %[ftmp7], %[ftmp1] \n\t"
|
|
|
|
|
"pcmpgth %[ftmp8], %[ftmp8], %[ftmp2] \n\t"
|
libavcodec/mips: Fix specification of instruction name
1.'xor,or,and' to 'pxor,por,pand'. In the case of operating FPR,
gcc supports both of them, clang only supports the second type.
2.'dsrl,srl' to 'ssrld,ssrlw'. In the case of operating FPR, gcc
supports both of them, clang only supports the second type.
Signed-off-by: Jin Bo <jinbo@loongson.cn>
Reviewed-by: yinshiyou-hf@loongson.cn
Signed-off-by: Michael Niedermayer <michael@niedermayer.cc>
2021-05-28 04:04:39 +02:00
|
|
|
"pxor %[ftmp1], %[ftmp1], %[ftmp7] \n\t"
|
|
|
|
|
"pxor %[ftmp2], %[ftmp2], %[ftmp8] \n\t"
|
2016-05-17 07:08:38 +02:00
|
|
|
"psubh %[ftmp1], %[ftmp1], %[ftmp7] \n\t"
|
|
|
|
|
"psubh %[ftmp2], %[ftmp2], %[ftmp8] \n\t"
|
|
|
|
|
"pmullh %[ftmp1], %[ftmp1], %[ftmp5] \n\t"
|
|
|
|
|
"pmullh %[ftmp2], %[ftmp2], %[ftmp6] \n\t"
|
libavcodec/mips: Fix specification of instruction name
1.'xor,or,and' to 'pxor,por,pand'. In the case of operating FPR,
gcc supports both of them, clang only supports the second type.
2.'dsrl,srl' to 'ssrld,ssrlw'. In the case of operating FPR, gcc
supports both of them, clang only supports the second type.
Signed-off-by: Jin Bo <jinbo@loongson.cn>
Reviewed-by: yinshiyou-hf@loongson.cn
Signed-off-by: Michael Niedermayer <michael@niedermayer.cc>
2021-05-28 04:04:39 +02:00
|
|
|
"pxor %[ftmp5], %[ftmp5], %[ftmp5] \n\t"
|
|
|
|
|
"pxor %[ftmp6], %[ftmp6], %[ftmp6] \n\t"
|
2016-05-17 07:08:38 +02:00
|
|
|
"pcmpeqh %[ftmp5], %[ftmp5], %[ftmp3] \n\t"
|
|
|
|
|
"dli %[tmp0], 0x03 \n\t"
|
|
|
|
|
"pcmpeqh %[ftmp6] , %[ftmp6], %[ftmp4] \n\t"
|
|
|
|
|
"mtc1 %[tmp0], %[ftmp3] \n\t"
|
|
|
|
|
"psrah %[ftmp1], %[ftmp1], %[ftmp3] \n\t"
|
|
|
|
|
"psrah %[ftmp2], %[ftmp2], %[ftmp3] \n\t"
|
libavcodec/mips: Fix specification of instruction name
1.'xor,or,and' to 'pxor,por,pand'. In the case of operating FPR,
gcc supports both of them, clang only supports the second type.
2.'dsrl,srl' to 'ssrld,ssrlw'. In the case of operating FPR, gcc
supports both of them, clang only supports the second type.
Signed-off-by: Jin Bo <jinbo@loongson.cn>
Reviewed-by: yinshiyou-hf@loongson.cn
Signed-off-by: Michael Niedermayer <michael@niedermayer.cc>
2021-05-28 04:04:39 +02:00
|
|
|
"pxor %[ftmp1], %[ftmp1], %[ftmp7] \n\t"
|
|
|
|
|
"pxor %[ftmp2], %[ftmp2], %[ftmp8] \n\t"
|
2016-05-17 07:08:38 +02:00
|
|
|
"psubh %[ftmp1], %[ftmp1], %[ftmp7] \n\t"
|
|
|
|
|
"psubh %[ftmp2], %[ftmp2], %[ftmp8] \n\t"
|
|
|
|
|
"pandn %[ftmp5], %[ftmp5], %[ftmp1] \n\t"
|
|
|
|
|
"pandn %[ftmp6], %[ftmp6], %[ftmp2] \n\t"
|
2016-10-10 10:09:12 +02:00
|
|
|
MMI_SDXC1(%[ftmp5], %[addr0], %[block], 0x00)
|
|
|
|
|
MMI_SDXC1(%[ftmp6], %[addr0], %[block], 0x08)
|
2019-05-24 04:26:43 +02:00
|
|
|
PTR_ADDIU "%[addr0], %[addr0], 0x10 \n\t"
|
2016-05-17 07:08:38 +02:00
|
|
|
"blez %[addr0], 1b \n\t"
|
|
|
|
|
: [ftmp0]"=&f"(ftmp[0]), [ftmp1]"=&f"(ftmp[1]),
|
|
|
|
|
[ftmp2]"=&f"(ftmp[2]), [ftmp3]"=&f"(ftmp[3]),
|
|
|
|
|
[ftmp4]"=&f"(ftmp[4]), [ftmp5]"=&f"(ftmp[5]),
|
|
|
|
|
[ftmp6]"=&f"(ftmp[6]), [ftmp7]"=&f"(ftmp[7]),
|
|
|
|
|
[ftmp8]"=&f"(ftmp[8]), [ftmp9]"=&f"(ftmp[9]),
|
|
|
|
|
[tmp0]"=&r"(tmp[0]),
|
2016-10-10 10:09:12 +02:00
|
|
|
RESTRICT_ASM_ALL64
|
|
|
|
|
RESTRICT_ASM_ADDRT
|
2016-05-17 07:08:38 +02:00
|
|
|
[addr0]"=&r"(addr[0])
|
|
|
|
|
: [block]"r"((mips_reg)(block+nCoeffs)),
|
|
|
|
|
[quant]"r"((mips_reg)(quant_matrix+nCoeffs)),
|
|
|
|
|
[nCoeffs]"r"((mips_reg)(2*(-nCoeffs))),
|
|
|
|
|
[qscale]"r"(qscale)
|
|
|
|
|
: "memory"
|
2015-09-02 12:01:00 +02:00
|
|
|
);
|
|
|
|
|
|
|
|
|
|
block[0]= block0;
|
|
|
|
|
}
|
2016-05-17 07:08:38 +02:00
|
|
|
|
|
|
|
|
void ff_denoise_dct_mmi(MpegEncContext *s, int16_t *block)
|
|
|
|
|
{
|
|
|
|
|
const int intra = s->mb_intra;
|
|
|
|
|
int *sum = s->dct_error_sum[intra];
|
|
|
|
|
uint16_t *offset = s->dct_offset[intra];
|
|
|
|
|
double ftmp[8];
|
|
|
|
|
mips_reg addr[1];
|
2016-10-10 10:09:12 +02:00
|
|
|
DECLARE_VAR_ALL64;
|
2016-05-17 07:08:38 +02:00
|
|
|
|
|
|
|
|
s->dct_count[intra]++;
|
|
|
|
|
|
|
|
|
|
__asm__ volatile(
|
libavcodec/mips: Fix specification of instruction name
1.'xor,or,and' to 'pxor,por,pand'. In the case of operating FPR,
gcc supports both of them, clang only supports the second type.
2.'dsrl,srl' to 'ssrld,ssrlw'. In the case of operating FPR, gcc
supports both of them, clang only supports the second type.
Signed-off-by: Jin Bo <jinbo@loongson.cn>
Reviewed-by: yinshiyou-hf@loongson.cn
Signed-off-by: Michael Niedermayer <michael@niedermayer.cc>
2021-05-28 04:04:39 +02:00
|
|
|
"pxor %[ftmp0], %[ftmp0], %[ftmp0] \n\t"
|
2016-05-17 07:08:38 +02:00
|
|
|
"1: \n\t"
|
2016-10-10 10:09:12 +02:00
|
|
|
MMI_LDC1(%[ftmp1], %[block], 0x00)
|
libavcodec/mips: Fix specification of instruction name
1.'xor,or,and' to 'pxor,por,pand'. In the case of operating FPR,
gcc supports both of them, clang only supports the second type.
2.'dsrl,srl' to 'ssrld,ssrlw'. In the case of operating FPR, gcc
supports both of them, clang only supports the second type.
Signed-off-by: Jin Bo <jinbo@loongson.cn>
Reviewed-by: yinshiyou-hf@loongson.cn
Signed-off-by: Michael Niedermayer <michael@niedermayer.cc>
2021-05-28 04:04:39 +02:00
|
|
|
"pxor %[ftmp2], %[ftmp2], %[ftmp2] \n\t"
|
2016-10-10 10:09:12 +02:00
|
|
|
MMI_LDC1(%[ftmp3], %[block], 0x08)
|
libavcodec/mips: Fix specification of instruction name
1.'xor,or,and' to 'pxor,por,pand'. In the case of operating FPR,
gcc supports both of them, clang only supports the second type.
2.'dsrl,srl' to 'ssrld,ssrlw'. In the case of operating FPR, gcc
supports both of them, clang only supports the second type.
Signed-off-by: Jin Bo <jinbo@loongson.cn>
Reviewed-by: yinshiyou-hf@loongson.cn
Signed-off-by: Michael Niedermayer <michael@niedermayer.cc>
2021-05-28 04:04:39 +02:00
|
|
|
"pxor %[ftmp4], %[ftmp4], %[ftmp4] \n\t"
|
2016-05-17 07:08:38 +02:00
|
|
|
"pcmpgth %[ftmp2], %[ftmp2], %[ftmp1] \n\t"
|
|
|
|
|
"pcmpgth %[ftmp4], %[ftmp4], %[ftmp3] \n\t"
|
libavcodec/mips: Fix specification of instruction name
1.'xor,or,and' to 'pxor,por,pand'. In the case of operating FPR,
gcc supports both of them, clang only supports the second type.
2.'dsrl,srl' to 'ssrld,ssrlw'. In the case of operating FPR, gcc
supports both of them, clang only supports the second type.
Signed-off-by: Jin Bo <jinbo@loongson.cn>
Reviewed-by: yinshiyou-hf@loongson.cn
Signed-off-by: Michael Niedermayer <michael@niedermayer.cc>
2021-05-28 04:04:39 +02:00
|
|
|
"pxor %[ftmp1], %[ftmp1], %[ftmp2] \n\t"
|
|
|
|
|
"pxor %[ftmp3], %[ftmp3], %[ftmp4] \n\t"
|
2016-05-17 07:08:38 +02:00
|
|
|
"psubh %[ftmp1], %[ftmp1], %[ftmp2] \n\t"
|
|
|
|
|
"psubh %[ftmp3], %[ftmp3], %[ftmp4] \n\t"
|
2016-10-10 10:09:12 +02:00
|
|
|
MMI_LDC1(%[ftmp6], %[offset], 0x00)
|
2016-05-17 07:08:38 +02:00
|
|
|
"mov.d %[ftmp5], %[ftmp1] \n\t"
|
|
|
|
|
"psubush %[ftmp1], %[ftmp1], %[ftmp6] \n\t"
|
2016-10-10 10:09:12 +02:00
|
|
|
MMI_LDC1(%[ftmp6], %[offset], 0x08)
|
2016-05-17 07:08:38 +02:00
|
|
|
"mov.d %[ftmp7], %[ftmp3] \n\t"
|
|
|
|
|
"psubush %[ftmp3], %[ftmp3], %[ftmp6] \n\t"
|
libavcodec/mips: Fix specification of instruction name
1.'xor,or,and' to 'pxor,por,pand'. In the case of operating FPR,
gcc supports both of them, clang only supports the second type.
2.'dsrl,srl' to 'ssrld,ssrlw'. In the case of operating FPR, gcc
supports both of them, clang only supports the second type.
Signed-off-by: Jin Bo <jinbo@loongson.cn>
Reviewed-by: yinshiyou-hf@loongson.cn
Signed-off-by: Michael Niedermayer <michael@niedermayer.cc>
2021-05-28 04:04:39 +02:00
|
|
|
"pxor %[ftmp1], %[ftmp1], %[ftmp2] \n\t"
|
|
|
|
|
"pxor %[ftmp3], %[ftmp3], %[ftmp4] \n\t"
|
2016-05-17 07:08:38 +02:00
|
|
|
"psubh %[ftmp1], %[ftmp1], %[ftmp2] \n\t"
|
|
|
|
|
"psubh %[ftmp3], %[ftmp3], %[ftmp4] \n\t"
|
2016-10-10 10:09:12 +02:00
|
|
|
MMI_SDC1(%[ftmp1], %[block], 0x00)
|
|
|
|
|
MMI_SDC1(%[ftmp3], %[block], 0x08)
|
2016-05-17 07:08:38 +02:00
|
|
|
"mov.d %[ftmp1], %[ftmp5] \n\t"
|
|
|
|
|
"mov.d %[ftmp3], %[ftmp7] \n\t"
|
|
|
|
|
"punpcklhw %[ftmp5], %[ftmp5], %[ftmp0] \n\t"
|
|
|
|
|
"punpckhhw %[ftmp1], %[ftmp1], %[ftmp0] \n\t"
|
|
|
|
|
"punpcklhw %[ftmp7], %[ftmp7], %[ftmp0] \n\t"
|
|
|
|
|
"punpckhhw %[ftmp3], %[ftmp3], %[ftmp0] \n\t"
|
2016-10-10 10:09:12 +02:00
|
|
|
MMI_LDC1(%[ftmp2], %[sum], 0x00)
|
2016-05-17 07:08:38 +02:00
|
|
|
"paddw %[ftmp5], %[ftmp5], %[ftmp2] \n\t"
|
2016-10-10 10:09:12 +02:00
|
|
|
MMI_LDC1(%[ftmp2], %[sum], 0x08)
|
2016-05-17 07:08:38 +02:00
|
|
|
"paddw %[ftmp1], %[ftmp1], %[ftmp2] \n\t"
|
2016-10-10 10:09:12 +02:00
|
|
|
MMI_LDC1(%[ftmp2], %[sum], 0x10)
|
2016-05-17 07:08:38 +02:00
|
|
|
"paddw %[ftmp7], %[ftmp7], %[ftmp2] \n\t"
|
2016-10-10 10:09:12 +02:00
|
|
|
MMI_LDC1(%[ftmp2], %[sum], 0x18)
|
2016-05-17 07:08:38 +02:00
|
|
|
"paddw %[ftmp3], %[ftmp3], %[ftmp2] \n\t"
|
2016-10-10 10:09:12 +02:00
|
|
|
MMI_SDC1(%[ftmp5], %[sum], 0x00)
|
|
|
|
|
MMI_SDC1(%[ftmp1], %[sum], 0x08)
|
|
|
|
|
MMI_SDC1(%[ftmp7], %[sum], 0x10)
|
|
|
|
|
MMI_SDC1(%[ftmp3], %[sum], 0x18)
|
2016-05-17 07:08:38 +02:00
|
|
|
PTR_ADDIU "%[block], %[block], 0x10 \n\t"
|
|
|
|
|
PTR_ADDIU "%[sum], %[sum], 0x20 \n\t"
|
|
|
|
|
PTR_SUBU "%[addr0], %[block1], %[block] \n\t"
|
|
|
|
|
PTR_ADDIU "%[offset], %[offset], 0x10 \n\t"
|
|
|
|
|
"bgtz %[addr0], 1b \n\t"
|
|
|
|
|
: [ftmp0]"=&f"(ftmp[0]), [ftmp1]"=&f"(ftmp[1]),
|
|
|
|
|
[ftmp2]"=&f"(ftmp[2]), [ftmp3]"=&f"(ftmp[3]),
|
|
|
|
|
[ftmp4]"=&f"(ftmp[4]), [ftmp5]"=&f"(ftmp[5]),
|
|
|
|
|
[ftmp6]"=&f"(ftmp[6]), [ftmp7]"=&f"(ftmp[7]),
|
2016-10-10 10:09:12 +02:00
|
|
|
RESTRICT_ASM_ALL64
|
2016-05-17 07:08:38 +02:00
|
|
|
[addr0]"=&r"(addr[0]),
|
|
|
|
|
[block]"+&r"(block), [sum]"+&r"(sum),
|
|
|
|
|
[offset]"+&r"(offset)
|
|
|
|
|
: [block1]"r"(block+64)
|
|
|
|
|
: "memory"
|
|
|
|
|
);
|
|
|
|
|
}
|
