2010-02-22 14:20:31 +02:00
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/*
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* ARM NEON optimised integer operations
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* Copyright (c) 2009 Kostya Shishkov
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*
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* This file is part of FFmpeg.
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*
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* FFmpeg is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* FFmpeg is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with FFmpeg; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include "asm.S"
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preserve8
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.fpu neon
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function ff_scalarproduct_int16_neon, export=1
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vmov.i16 q0, #0
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vmov.i16 q1, #0
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vmov.i16 q2, #0
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vmov.i16 q3, #0
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negs r3, r3
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beq 2f
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vdup.s32 q12, r3
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1: vld1.16 {d16-d17}, [r0]!
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vld1.16 {d20-d21}, [r1,:128]!
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vmull.s16 q12, d16, d20
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vld1.16 {d18-d19}, [r0]!
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vmull.s16 q13, d17, d21
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vld1.16 {d22-d23}, [r1,:128]!
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vmull.s16 q14, d18, d22
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vmull.s16 q15, d19, d23
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vshl.s32 q8, q12, q12
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vshl.s32 q9, q13, q12
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vadd.s32 q0, q0, q8
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vshl.s32 q10, q14, q12
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vadd.s32 q1, q1, q9
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vshl.s32 q11, q15, q12
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vadd.s32 q2, q2, q10
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vadd.s32 q3, q3, q11
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subs r2, r2, #16
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bne 1b
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b 3f
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2: vld1.16 {d16-d17}, [r0]!
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vld1.16 {d20-d21}, [r1,:128]!
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vmlal.s16 q0, d16, d20
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vld1.16 {d18-d19}, [r0]!
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vmlal.s16 q1, d17, d21
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vld1.16 {d22-d23}, [r1,:128]!
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vmlal.s16 q2, d18, d22
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vmlal.s16 q3, d19, d23
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subs r2, r2, #16
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bne 2b
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3: vpadd.s32 d16, d0, d1
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vpadd.s32 d17, d2, d3
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vpadd.s32 d10, d4, d5
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vpadd.s32 d11, d6, d7
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vpadd.s32 d0, d16, d17
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vpadd.s32 d1, d10, d11
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vpadd.s32 d2, d0, d1
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vpaddl.s32 d3, d2
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vmov.32 r0, d3[0]
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bx lr
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2010-03-09 18:17:56 +02:00
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endfunc
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2010-02-22 14:20:31 +02:00
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@ scalarproduct_and_madd_int16(/*aligned*/v0,v1,v2,order,mul)
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function ff_scalarproduct_and_madd_int16_neon, export=1
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vld1.16 {d28[],d29[]}, [sp]
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vmov.i16 q0, #0
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vmov.i16 q1, #0
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vmov.i16 q2, #0
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vmov.i16 q3, #0
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mov r12, r0
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1: vld1.16 {d16-d17}, [r0,:128]!
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vld1.16 {d18-d19}, [r1]!
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vld1.16 {d20-d21}, [r2]!
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vld1.16 {d22-d23}, [r0,:128]!
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vld1.16 {d24-d25}, [r1]!
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vld1.16 {d26-d27}, [r2]!
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vmul.s16 q10, q10, q14
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vmul.s16 q13, q13, q14
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vmlal.s16 q0, d16, d18
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vmlal.s16 q1, d17, d19
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vadd.s16 q10, q8, q10
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vadd.s16 q13, q11, q13
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vmlal.s16 q2, d22, d24
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vmlal.s16 q3, d23, d25
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vst1.16 {q10}, [r12,:128]!
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subs r3, r3, #16
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vst1.16 {q13}, [r12,:128]!
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bne 1b
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vpadd.s32 d16, d0, d1
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vpadd.s32 d17, d2, d3
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vpadd.s32 d10, d4, d5
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vpadd.s32 d11, d6, d7
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vpadd.s32 d0, d16, d17
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vpadd.s32 d1, d10, d11
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vpadd.s32 d2, d0, d1
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vpaddl.s32 d3, d2
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vmov.32 r0, d3[0]
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bx lr
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2010-03-09 18:17:56 +02:00
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endfunc
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