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FFmpeg/ffbuild/arch.mak

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build: Consistently handle conditional compilation for all optimization OBJS.
2012-03-28 00:10:02 +03:00
OBJS-$(HAVE_ARMV5TE) += $(ARMV5TE-OBJS) $(ARMV5TE-OBJS-yes)
OBJS-$(HAVE_ARMV6) += $(ARMV6-OBJS) $(ARMV6-OBJS-yes)
aarch64: add armv8 CPU flag
2014-04-05 14:46:51 +03:00
OBJS-$(HAVE_ARMV8) += $(ARMV8-OBJS) $(ARMV8-OBJS-yes)
arm: rename ARMVFP config symbol to VFP This is consistent with usual ARM nomenclature as well as with the VFPV3 and NEON symbols which both lack the ARM prefix. Signed-off-by: Mans Rullgard <mans@mansr.com>
2012-12-05 02:29:34 +03:00
OBJS-$(HAVE_VFP) += $(VFP-OBJS) $(VFP-OBJS-yes)
build: Consistently handle conditional compilation for all optimization OBJS.
2012-03-28 00:10:02 +03:00
OBJS-$(HAVE_NEON) += $(NEON-OBJS) $(NEON-OBJS-yes)
Optimization of AMR NB and WB decoders for MIPS AMR NB and WB decoders are optimized for MIPS architecture. Appropriate Makefiles are changed accordingly. Cnfigure script is changed in order to support optimizations. Optimizations are enabled by default when compiling is done for mips architecture. Appropriate cflags are automatically set. Support for several mips CPUs is added in configure script. New ffmpeg options are added for disabling optimizations. The FFMPEG option --disable-mipsfpu disables MIPS floating point optimizations. The FFMPEG option --disable-mips32r2 disables MIPS32R2 optimizations. The FFMPEG option --disable-mipsdspr1 disables MIPS DSP ASE R1 optimizations. The FFMPEG option --disable-mipsdspr2 disables MIPS DSP ASE R2 optimizations. Signed-off-by: Nedeljko Babic <nbabic@mips.com> Reviewed-by: Vitor Sessak <vitor1001@gmail.com> Signed-off-by: Michael Niedermayer <michaelni@gmx.at>
2012-06-04 19:02:56 +03:00
OBJS-$(HAVE_MIPSFPU) += $(MIPSFPU-OBJS) $(MIPSFPU-OBJS-yes)
mips: rename mipsdspr1 to mipsdsp Signed-off-by: Vicente Olivert Riera <Vincent.Riera@imgtec.com> Signed-off-by: Michael Niedermayer <michael@niedermayer.cc>
2015-12-03 15:22:16 +02:00
OBJS-$(HAVE_MIPSDSP) += $(MIPSDSP-OBJS) $(MIPSDSP-OBJS-yes)
Optimization of AMR NB and WB decoders for MIPS AMR NB and WB decoders are optimized for MIPS architecture. Appropriate Makefiles are changed accordingly. Cnfigure script is changed in order to support optimizations. Optimizations are enabled by default when compiling is done for mips architecture. Appropriate cflags are automatically set. Support for several mips CPUs is added in configure script. New ffmpeg options are added for disabling optimizations. The FFMPEG option --disable-mipsfpu disables MIPS floating point optimizations. The FFMPEG option --disable-mips32r2 disables MIPS32R2 optimizations. The FFMPEG option --disable-mipsdspr1 disables MIPS DSP ASE R1 optimizations. The FFMPEG option --disable-mipsdspr2 disables MIPS DSP ASE R2 optimizations. Signed-off-by: Nedeljko Babic <nbabic@mips.com> Reviewed-by: Vitor Sessak <vitor1001@gmail.com> Signed-off-by: Michael Niedermayer <michaelni@gmx.at>
2012-06-04 19:02:56 +03:00
OBJS-$(HAVE_MIPSDSPR2) += $(MIPSDSPR2-OBJS) $(MIPSDSPR2-OBJS-yes)
Makefile: Add support for MSA (MIPS-SIMD-Arch) Signed-off-by: Shivraj Patil <shivraj.patil@imgtec.com> Reviewed-by: Nedeljko Babic <Nedeljko.Babic@imgtec.com> Signed-off-by: Michael Niedermayer <michaelni@gmx.at>
2015-04-17 15:12:27 +02:00
OBJS-$(HAVE_MSA) += $(MSA-OBJS) $(MSA-OBJS-yes)
avutil: [loongarch] Add support for loongarch SIMD. LSX and LASX is loongarch SIMD extention. They are enabled by default if compiler support it, and can be disabled with '--disable-lsx' '--disable-lasx'. Change-Id: Ie2608ea61dbd9b7fffadbf0ec2348bad6c124476 Reviewed-by: Shiyou Yin <yinshiyou-hf@loongson.cn> Reviewed-by: guxiwei <guxiwei-hf@loongson.cn> Signed-off-by: Michael Niedermayer <michael@niedermayer.cc>
2021-12-15 05:51:04 +02:00
OBJS-$(HAVE_MMI) += $(MMI-OBJS) $(MMI-OBJS-yes)
OBJS-$(HAVE_LSX) += $(LSX-OBJS) $(LSX-OBJS-yes)
OBJS-$(HAVE_LASX) += $(LASX-OBJS) $(LASX-OBJS-yes)
build: Consistently handle conditional compilation for all optimization OBJS.
2012-03-28 00:10:02 +03:00
OBJS-$(HAVE_ALTIVEC) += $(ALTIVEC-OBJS) $(ALTIVEC-OBJS-yes)
ppc: vsx: Implement float_dsp
2015-05-11 02:44:10 +02:00
OBJS-$(HAVE_VSX) += $(VSX-OBJS) $(VSX-OBJS-yes)
build: Consistently handle conditional compilation for all optimization OBJS.
2012-03-28 00:10:02 +03:00
riscv: test for assembler support This should fix the build on LLVM 16 and earlier, at the cost of turning all non-RVV optimisations off.
2023-12-05 17:54:26 +02:00
OBJS-$(HAVE_RV) += $(RV-OBJS) $(RV-OBJS-yes)
configure: probe RISC-V Vector extension
2022-09-26 16:52:26 +02:00
OBJS-$(HAVE_RVV) += $(RVV-OBJS) $(RVV-OBJS-yes)
riscv: add Zvbb vector bit manipulation extension
2024-05-07 21:08:38 +02:00
OBJS-$(HAVE_RV_ZVBB) += $(RVVB-OBJS) $(RVVB-OBJS-yes)
configure: probe RISC-V Vector extension
2022-09-26 16:52:26 +02:00
build: Consistently handle conditional compilation for all optimization OBJS.
2012-03-28 00:10:02 +03:00
OBJS-$(HAVE_MMX) += $(MMX-OBJS) $(MMX-OBJS-yes)
build: Generalize yasm/nasm-related variable names None of them are specific to the YASM assembler. (Cherry-picked from libav commit 39e208f4d4756367c7cd2d581847e0c1b8a429c1) Signed-off-by: James Almer <jamrial@gmail.com>
2016-10-08 16:18:33 +02:00
OBJS-$(HAVE_X86ASM) += $(X86ASM-OBJS) $(X86ASM-OBJS-yes)
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