2018-09-18 04:59:41 +02:00
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/*
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* Loongson SIMD optimized h264chroma
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*
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* Copyright (c) 2018 Loongson Technology Corporation Limited
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2021-04-12 17:37:02 +02:00
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* Contributed by Shiyou Yin <yinshiyou-hf@loongson.cn>
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* Gu Xiwei(guxiwei-hf@loongson.cn)
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2018-09-18 04:59:41 +02:00
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*
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* This file is part of FFmpeg.
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*
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* FFmpeg is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* FFmpeg is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with FFmpeg; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef AVCODEC_MIPS_CABAC_H
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#define AVCODEC_MIPS_CABAC_H
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2021-04-14 15:11:43 +02:00
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#include "libavutil/attributes.h"
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2018-09-18 04:59:41 +02:00
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#include "libavcodec/cabac.h"
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2021-04-12 17:37:02 +02:00
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#include "libavutil/mips/mmiutils.h"
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2018-09-18 04:59:41 +02:00
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#include "config.h"
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2022-12-01 09:00:06 +02:00
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#if !HAVE_MIPS32R6 && !HAVE_MIPS64R6
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2018-09-18 04:59:41 +02:00
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#define get_cabac_inline get_cabac_inline_mips
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2020-04-12 03:54:33 +02:00
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static av_always_inline int get_cabac_inline_mips(CABACContext *c,
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2021-04-12 17:37:02 +02:00
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uint8_t * const state){
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2018-09-18 04:59:41 +02:00
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mips_reg tmp0, tmp1, tmp2, bit;
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__asm__ volatile (
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"lbu %[bit], 0(%[state]) \n\t"
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"and %[tmp0], %[c_range], 0xC0 \n\t"
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2021-04-12 17:37:02 +02:00
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PTR_SLL "%[tmp0], %[tmp0], 0x01 \n\t"
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2018-09-18 04:59:41 +02:00
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PTR_ADDU "%[tmp0], %[tmp0], %[tables] \n\t"
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PTR_ADDU "%[tmp0], %[tmp0], %[bit] \n\t"
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/* tmp1: RangeLPS */
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"lbu %[tmp1], %[lps_off](%[tmp0]) \n\t"
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PTR_SUBU "%[c_range], %[c_range], %[tmp1] \n\t"
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PTR_SLL "%[tmp0], %[c_range], 0x11 \n\t"
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2021-04-12 17:37:02 +02:00
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"slt %[tmp2], %[tmp0], %[c_low] \n\t"
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2018-09-18 04:59:41 +02:00
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"beqz %[tmp2], 1f \n\t"
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2021-04-12 17:37:02 +02:00
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"move %[c_range], %[tmp1] \n\t"
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"not %[bit], %[bit] \n\t"
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2018-09-18 04:59:41 +02:00
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PTR_SUBU "%[c_low], %[c_low], %[tmp0] \n\t"
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"1: \n\t"
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/* tmp1: *state */
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PTR_ADDU "%[tmp0], %[tables], %[bit] \n\t"
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"lbu %[tmp1], %[mlps_off](%[tmp0]) \n\t"
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/* tmp2: lps_mask */
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PTR_ADDU "%[tmp0], %[tables], %[c_range] \n\t"
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"lbu %[tmp2], %[norm_off](%[tmp0]) \n\t"
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"sb %[tmp1], 0(%[state]) \n\t"
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"and %[bit], %[bit], 0x01 \n\t"
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PTR_SLL "%[c_range], %[c_range], %[tmp2] \n\t"
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PTR_SLL "%[c_low], %[c_low], %[tmp2] \n\t"
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2021-04-12 17:37:02 +02:00
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"and %[tmp1], %[c_low], %[cabac_mask] \n\t"
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"bnez %[tmp1], 1f \n\t"
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PTR_ADDIU "%[tmp0], %[c_low], -0X01 \n\t"
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2018-09-18 04:59:41 +02:00
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"xor %[tmp0], %[c_low], %[tmp0] \n\t"
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PTR_SRA "%[tmp0], %[tmp0], 0x0f \n\t"
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PTR_ADDU "%[tmp0], %[tmp0], %[tables] \n\t"
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2021-04-12 17:37:02 +02:00
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/* tmp2: ff_h264_norm_shift[x >> (CABAC_BITS - 1)] */
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2018-09-18 04:59:41 +02:00
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"lbu %[tmp2], %[norm_off](%[tmp0]) \n\t"
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2021-04-12 17:37:02 +02:00
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#if HAVE_BIGENDIAN
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"lhu %[tmp0], 0(%[c_bytestream]) \n\t"
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2018-09-18 04:59:41 +02:00
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#else
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2021-04-12 17:37:02 +02:00
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"lhu %[tmp0], 0(%[c_bytestream]) \n\t"
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2021-07-23 07:53:44 +02:00
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#if HAVE_MIPS32R2 || HAVE_MIPS64R2
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2021-04-12 17:37:02 +02:00
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"wsbh %[tmp0], %[tmp0] \n\t"
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2021-07-23 07:53:44 +02:00
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#else
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"and %[tmp1], %[tmp0], 0xff00ff00 \n\t"
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"srl %[tmp1], %[tmp1], 8 \n\t"
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"and %[tmp0], %[tmp0], 0x00ff00ff \n\t"
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"sll %[tmp0], %[tmp0], 8 \n\t"
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"or %[tmp0], %[tmp0], %[tmp1] \n\t"
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#endif
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2018-09-18 04:59:41 +02:00
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#endif
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2021-04-12 17:37:02 +02:00
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PTR_SLL "%[tmp0], %[tmp0], 0x01 \n\t"
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2018-09-18 04:59:41 +02:00
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PTR_SUBU "%[tmp0], %[tmp0], %[cabac_mask] \n\t"
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"li %[tmp1], 0x07 \n\t"
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PTR_SUBU "%[tmp1], %[tmp1], %[tmp2] \n\t"
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PTR_SLL "%[tmp0], %[tmp0], %[tmp1] \n\t"
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PTR_ADDU "%[c_low], %[c_low], %[tmp0] \n\t"
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2021-04-12 17:37:02 +02:00
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#if UNCHECKED_BITSTREAM_READER
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PTR_ADDIU "%[c_bytestream], %[c_bytestream], 0x02 \n\t"
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#else
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"slt %[tmp0], %[c_bytestream], %[c_bytestream_end] \n\t"
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PTR_ADDIU "%[tmp2], %[c_bytestream], 0x02 \n\t"
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"movn %[c_bytestream], %[tmp2], %[tmp0] \n\t"
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2018-09-18 04:59:41 +02:00
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#endif
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"1: \n\t"
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: [bit]"=&r"(bit), [tmp0]"=&r"(tmp0), [tmp1]"=&r"(tmp1), [tmp2]"=&r"(tmp2),
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[c_range]"+&r"(c->range), [c_low]"+&r"(c->low),
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[c_bytestream]"+&r"(c->bytestream)
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: [state]"r"(state), [tables]"r"(ff_h264_cabac_tables),
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#if !UNCHECKED_BITSTREAM_READER
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[c_bytestream_end]"r"(c->bytestream_end),
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#endif
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[lps_off]"i"(H264_LPS_RANGE_OFFSET),
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[mlps_off]"i"(H264_MLPS_STATE_OFFSET + 128),
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[norm_off]"i"(H264_NORM_SHIFT_OFFSET),
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2020-07-29 12:11:00 +02:00
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[cabac_mask]"r"(CABAC_MASK)
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2018-09-18 04:59:41 +02:00
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: "memory"
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);
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return bit;
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}
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2021-04-12 17:37:02 +02:00
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#define get_cabac_bypass get_cabac_bypass_mips
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static av_always_inline int get_cabac_bypass_mips(CABACContext *c)
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{
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mips_reg tmp0, tmp1;
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int res = 0;
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__asm__ volatile(
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PTR_SLL "%[c_low], %[c_low], 0x01 \n\t"
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"and %[tmp0], %[c_low], %[cabac_mask] \n\t"
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"bnez %[tmp0], 1f \n\t"
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#if HAVE_BIGENDIAN
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"lhu %[tmp1], 0(%[c_bytestream]) \n\t"
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#else
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"lhu %[tmp1], 0(%[c_bytestream]) \n\t"
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2021-07-23 07:53:44 +02:00
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#if HAVE_MIPS32R2 || HAVE_MIPS64R2
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2021-04-12 17:37:02 +02:00
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"wsbh %[tmp1], %[tmp1] \n\t"
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2021-07-23 07:53:44 +02:00
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#else
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"and %[tmp0], %[tmp1], 0xff00ff00 \n\t"
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"srl %[tmp0], %[tmp0], 8 \n\t"
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"and %[tmp1], %[tmp1], 0x00ff00ff \n\t"
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"sll %[tmp1], %[tmp1], 8 \n\t"
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"or %[tmp1], %[tmp1], %[tmp0] \n\t"
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#endif
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2021-04-12 17:37:02 +02:00
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#endif
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PTR_SLL "%[tmp1], %[tmp1], 0x01 \n\t"
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PTR_SUBU "%[tmp1], %[tmp1], %[cabac_mask] \n\t"
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PTR_ADDU "%[c_low], %[c_low], %[tmp1] \n\t"
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#if UNCHECKED_BITSTREAM_READER
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PTR_ADDIU "%[c_bytestream], %[c_bytestream], 0x02 \n\t"
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#else
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"slt %[tmp0], %[c_bytestream], %[c_bytestream_end] \n\t"
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PTR_ADDIU "%[tmp1], %[c_bytestream], 0x02 \n\t"
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"movn %[c_bytestream], %[tmp1], %[tmp0] \n\t"
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#endif
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"1: \n\t"
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PTR_SLL "%[tmp1], %[c_range], 0x11 \n\t"
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"slt %[tmp0], %[c_low], %[tmp1] \n\t"
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PTR_SUBU "%[tmp1], %[c_low], %[tmp1] \n\t"
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"movz %[res], %[one], %[tmp0] \n\t"
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"movz %[c_low], %[tmp1], %[tmp0] \n\t"
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: [tmp0]"=&r"(tmp0), [tmp1]"=&r"(tmp1), [res]"+&r"(res),
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[c_range]"+&r"(c->range), [c_low]"+&r"(c->low),
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[c_bytestream]"+&r"(c->bytestream)
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: [cabac_mask]"r"(CABAC_MASK),
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#if !UNCHECKED_BITSTREAM_READER
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[c_bytestream_end]"r"(c->bytestream_end),
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#endif
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[one]"r"(0x01)
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: "memory"
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);
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return res;
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}
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#define get_cabac_bypass_sign get_cabac_bypass_sign_mips
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static av_always_inline int get_cabac_bypass_sign_mips(CABACContext *c, int val)
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{
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mips_reg tmp0, tmp1;
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int res = val;
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__asm__ volatile(
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PTR_SLL "%[c_low], %[c_low], 0x01 \n\t"
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"and %[tmp0], %[c_low], %[cabac_mask] \n\t"
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"bnez %[tmp0], 1f \n\t"
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#if HAVE_BIGENDIAN
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"lhu %[tmp1], 0(%[c_bytestream]) \n\t"
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#else
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"lhu %[tmp1], 0(%[c_bytestream]) \n\t"
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2021-07-23 07:53:44 +02:00
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#if HAVE_MIPS32R2 || HAVE_MIPS64R2
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2021-04-12 17:37:02 +02:00
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"wsbh %[tmp1], %[tmp1] \n\t"
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2021-07-23 07:53:44 +02:00
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#else
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"and %[tmp0], %[tmp1], 0xff00ff00 \n\t"
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"srl %[tmp0], %[tmp0], 8 \n\t"
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"and %[tmp1], %[tmp1], 0x00ff00ff \n\t"
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"sll %[tmp1], %[tmp1], 8 \n\t"
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"or %[tmp1], %[tmp1], %[tmp0] \n\t"
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#endif
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2021-04-12 17:37:02 +02:00
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#endif
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PTR_SLL "%[tmp1], %[tmp1], 0x01 \n\t"
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PTR_SUBU "%[tmp1], %[tmp1], %[cabac_mask] \n\t"
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PTR_ADDU "%[c_low], %[c_low], %[tmp1] \n\t"
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#if UNCHECKED_BITSTREAM_READER
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PTR_ADDIU "%[c_bytestream], %[c_bytestream], 0x02 \n\t"
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#else
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"slt %[tmp0], %[c_bytestream], %[c_bytestream_end] \n\t"
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PTR_ADDIU "%[tmp1], %[c_bytestream], 0x02 \n\t"
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"movn %[c_bytestream], %[tmp1], %[tmp0] \n\t"
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#endif
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"1: \n\t"
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PTR_SLL "%[tmp1], %[c_range], 0x11 \n\t"
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"slt %[tmp0], %[c_low], %[tmp1] \n\t"
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PTR_SUBU "%[tmp1], %[c_low], %[tmp1] \n\t"
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"movz %[c_low], %[tmp1], %[tmp0] \n\t"
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PTR_SUBU "%[tmp1], %[zero], %[res] \n\t"
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"movn %[res], %[tmp1], %[tmp0] \n\t"
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: [tmp0]"=&r"(tmp0), [tmp1]"=&r"(tmp1), [res]"+&r"(res),
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[c_range]"+&r"(c->range), [c_low]"+&r"(c->low),
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[c_bytestream]"+&r"(c->bytestream)
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: [cabac_mask]"r"(CABAC_MASK),
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#if !UNCHECKED_BITSTREAM_READER
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[c_bytestream_end]"r"(c->bytestream_end),
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#endif
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[zero]"r"(0x0)
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: "memory"
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);
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return res;
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}
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2022-12-01 09:00:06 +02:00
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#endif /* !HAVE_MIPS32R6 && !HAVE_MIPS64R6 */
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2018-09-18 04:59:41 +02:00
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#endif /* AVCODEC_MIPS_CABAC_H */
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