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Code Issues Releases Activity

riscv/vvc: fix UNDEF whilst initialising DSP

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The current triggers an illegal instruction if the CPU does not support
vectors.
This commit is contained in:
Rémi Denis-Courmont 2024-10-12 08:30:37 +03:00
parent 5557c673ea
commit 1eb026dd8b
1 changed files with 7 additions and 5 deletions
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12
libavcodec/riscv/vvc/vvcdsp_init.c
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@ -41,10 +41,13 @@ void ff_vvc_dsp_init_riscv(VVCDSPContext *const c, const int bd)
{ {
#if HAVE_RVV #if HAVE_RVV
const int flags = av_get_cpu_flags(); const int flags = av_get_cpu_flags();
int vlenb = ff_get_rv_vlenb(); int vlenb;
if ((flags & AV_CPU_FLAG_RVV_I32) && (flags & AV_CPU_FLAG_RVB) && if (!(flags & AV_CPU_FLAG_RVV_I32) || !(flags & AV_CPU_FLAG_RVB))
vlenb >= 32) { return;
vlenb = ff_get_rv_vlenb();
if (vlenb >= 32) {
switch (bd) { switch (bd) {
case 8: case 8:
c->inter.avg = ff_vvc_avg_8_rvv_256; c->inter.avg = ff_vvc_avg_8_rvv_256;
@ -55,8 +58,7 @@ void ff_vvc_dsp_init_riscv(VVCDSPContext *const c, const int bd)
default: default:
break; break;
} }
} else if ((flags & AV_CPU_FLAG_RVV_I32) && (flags & AV_CPU_FLAG_RVB) && } else if (vlenb >= 16) {
vlenb >= 16) {
switch (bd) { switch (bd) {
case 8: case 8:
c->inter.avg = ff_vvc_avg_8_rvv_128; c->inter.avg = ff_vvc_avg_8_rvv_128;