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avcodec/vc1: Arm 32-bit NEON unescape fast path
checkasm benchmarks on 1.5 GHz Cortex-A72 are as follows. vc1dsp.vc1_unescape_buffer_c: 918624.7 vc1dsp.vc1_unescape_buffer_neon: 142958.0 Signed-off-by: Ben Avison <bavison@riscosopen.org> Signed-off-by: Martin Storsjö <martin@martin.st>
This commit is contained in:
Ben Avison
Martin Storsjö
parent
6eee650289
commit
23c92e14f5
@ -19,6 +19,7 @@
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#include <stdint.h>
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#include <stdint.h>
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#include "libavutil/attributes.h"
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#include "libavutil/attributes.h"
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#include "libavutil/intreadwrite.h"
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#include "libavcodec/vc1dsp.h"
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#include "libavcodec/vc1dsp.h"
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#include "vc1dsp.h"
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#include "vc1dsp.h"
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@ -84,6 +85,64 @@ void ff_put_vc1_chroma_mc4_neon(uint8_t *dst, uint8_t *src, ptrdiff_t stride,
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void ff_avg_vc1_chroma_mc4_neon(uint8_t *dst, uint8_t *src, ptrdiff_t stride,
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void ff_avg_vc1_chroma_mc4_neon(uint8_t *dst, uint8_t *src, ptrdiff_t stride,
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int h, int x, int y);
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int h, int x, int y);
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int ff_vc1_unescape_buffer_helper_neon(const uint8_t *src, int size, uint8_t *dst);
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static int vc1_unescape_buffer_neon(const uint8_t *src, int size, uint8_t *dst)
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{
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/* Dealing with starting and stopping, and removing escape bytes, are
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* comparatively less time-sensitive, so are more clearly expressed using
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* a C wrapper around the assembly inner loop. Note that we assume a
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* little-endian machine that supports unaligned loads. */
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int dsize = 0;
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while (size >= 4)
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{
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int found = 0;
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while (!found && (((uintptr_t) dst) & 7) && size >= 4)
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{
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found = (AV_RL32(src) &~ 0x03000000) == 0x00030000;
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if (!found)
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{
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*dst++ = *src++;
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--size;
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++dsize;
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}
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}
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if (!found)
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{
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int skip = size - ff_vc1_unescape_buffer_helper_neon(src, size, dst);
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dst += skip;
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src += skip;
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size -= skip;
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dsize += skip;
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while (!found && size >= 4)
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{
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found = (AV_RL32(src) &~ 0x03000000) == 0x00030000;
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if (!found)
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{
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*dst++ = *src++;
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--size;
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++dsize;
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}
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}
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}
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if (found)
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{
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*dst++ = *src++;
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*dst++ = *src++;
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++src;
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size -= 3;
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dsize += 2;
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}
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}
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while (size > 0)
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{
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*dst++ = *src++;
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--size;
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++dsize;
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}
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return dsize;
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}
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#define FN_ASSIGN(X, Y) \
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#define FN_ASSIGN(X, Y) \
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dsp->put_vc1_mspel_pixels_tab[0][X+4*Y] = ff_put_vc1_mspel_mc##X##Y##_16_neon; \
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dsp->put_vc1_mspel_pixels_tab[0][X+4*Y] = ff_put_vc1_mspel_mc##X##Y##_16_neon; \
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dsp->put_vc1_mspel_pixels_tab[1][X+4*Y] = ff_put_vc1_mspel_mc##X##Y##_neon
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dsp->put_vc1_mspel_pixels_tab[1][X+4*Y] = ff_put_vc1_mspel_mc##X##Y##_neon
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@ -130,4 +189,6 @@ av_cold void ff_vc1dsp_init_neon(VC1DSPContext *dsp)
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dsp->avg_no_rnd_vc1_chroma_pixels_tab[0] = ff_avg_vc1_chroma_mc8_neon;
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dsp->avg_no_rnd_vc1_chroma_pixels_tab[0] = ff_avg_vc1_chroma_mc8_neon;
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dsp->put_no_rnd_vc1_chroma_pixels_tab[1] = ff_put_vc1_chroma_mc4_neon;
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dsp->put_no_rnd_vc1_chroma_pixels_tab[1] = ff_put_vc1_chroma_mc4_neon;
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dsp->avg_no_rnd_vc1_chroma_pixels_tab[1] = ff_avg_vc1_chroma_mc4_neon;
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dsp->avg_no_rnd_vc1_chroma_pixels_tab[1] = ff_avg_vc1_chroma_mc4_neon;
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dsp->vc1_unescape_buffer = vc1_unescape_buffer_neon;
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}
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}
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@ -1804,3 +1804,121 @@ function ff_vc1_h_loop_filter16_neon, export=1
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4: vpop {d8-d15}
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4: vpop {d8-d15}
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pop {r4-r6,pc}
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pop {r4-r6,pc}
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endfunc
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endfunc
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@ Copy at most the specified number of bytes from source to destination buffer,
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@ stopping at a multiple of 16 bytes, none of which are the start of an escape sequence
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@ On entry:
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@ r0 -> source buffer
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@ r1 = max number of bytes to copy
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@ r2 -> destination buffer, optimally 8-byte aligned
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@ On exit:
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@ r0 = number of bytes not copied
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function ff_vc1_unescape_buffer_helper_neon, export=1
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@ Offset by 48 to screen out cases that are too short for us to handle,
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@ and also make it easy to test for loop termination, or to determine
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@ whether we need an odd number of half-iterations of the loop.
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subs r1, r1, #48
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bmi 90f
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@ Set up useful constants
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vmov.i32 q0, #0x3000000
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vmov.i32 q1, #0x30000
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tst r1, #16
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bne 1f
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vld1.8 {q8, q9}, [r0]!
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vbic q12, q8, q0
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vext.8 q13, q8, q9, #1
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vext.8 q14, q8, q9, #2
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vext.8 q15, q8, q9, #3
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veor q12, q12, q1
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vbic q13, q13, q0
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vbic q14, q14, q0
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vbic q15, q15, q0
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vceq.i32 q12, q12, #0
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veor q13, q13, q1
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veor q14, q14, q1
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veor q15, q15, q1
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vceq.i32 q13, q13, #0
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vceq.i32 q14, q14, #0
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vceq.i32 q15, q15, #0
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add r1, r1, #16
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b 3f
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1: vld1.8 {q10, q11}, [r0]!
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vbic q12, q10, q0
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vext.8 q13, q10, q11, #1
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vext.8 q14, q10, q11, #2
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vext.8 q15, q10, q11, #3
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veor q12, q12, q1
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vbic q13, q13, q0
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vbic q14, q14, q0
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vbic q15, q15, q0
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vceq.i32 q12, q12, #0
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veor q13, q13, q1
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veor q14, q14, q1
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veor q15, q15, q1
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vceq.i32 q13, q13, #0
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vceq.i32 q14, q14, #0
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vceq.i32 q15, q15, #0
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@ Drop through...
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2: vmov q8, q11
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vld1.8 {q9}, [r0]!
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vorr q13, q12, q13
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vorr q15, q14, q15
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vbic q12, q8, q0
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vorr q3, q13, q15
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vext.8 q13, q8, q9, #1
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vext.8 q14, q8, q9, #2
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vext.8 q15, q8, q9, #3
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veor q12, q12, q1
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vorr d6, d6, d7
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vbic q13, q13, q0
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vbic q14, q14, q0
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vbic q15, q15, q0
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vceq.i32 q12, q12, #0
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vmov r3, r12, d6
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veor q13, q13, q1
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veor q14, q14, q1
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veor q15, q15, q1
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vceq.i32 q13, q13, #0
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vceq.i32 q14, q14, #0
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vceq.i32 q15, q15, #0
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orrs r3, r3, r12
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bne 90f
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vst1.64 {q10}, [r2]!
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3: vmov q10, q9
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vld1.8 {q11}, [r0]!
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vorr q13, q12, q13
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vorr q15, q14, q15
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vbic q12, q10, q0
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vorr q3, q13, q15
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vext.8 q13, q10, q11, #1
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vext.8 q14, q10, q11, #2
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vext.8 q15, q10, q11, #3
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veor q12, q12, q1
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vorr d6, d6, d7
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vbic q13, q13, q0
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vbic q14, q14, q0
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vbic q15, q15, q0
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vceq.i32 q12, q12, #0
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vmov r3, r12, d6
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veor q13, q13, q1
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veor q14, q14, q1
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veor q15, q15, q1
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vceq.i32 q13, q13, #0
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vceq.i32 q14, q14, #0
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vceq.i32 q15, q15, #0
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orrs r3, r3, r12
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bne 91f
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vst1.64 {q8}, [r2]!
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subs r1, r1, #32
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bpl 2b
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90: add r0, r1, #48
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bx lr
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91: sub r1, r1, #16
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b 90b
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endfunc
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