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aarch64/vvc: Add sad
sad_8x16_c: 0.8 ( 1.00x) sad_8x16_neon: 0.2 ( 3.00x) sad_16x8_c: 0.5 ( 1.00x) sad_16x8_neon: 0.2 ( 2.00x) sad_16x16_c: 1.5 ( 1.00x) sad_16x16_neon: 0.2 ( 6.00x)
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5ac6925803
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@ -3,6 +3,7 @@ clean::
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OBJS-$(CONFIG_VVC_DECODER) += aarch64/vvc/dsp_init.o
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NEON-OBJS-$(CONFIG_VVC_DECODER) += aarch64/vvc/alf.o \
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aarch64/vvc/sad.o \
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aarch64/h26x/epel_neon.o \
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aarch64/h26x/qpel_neon.o \
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aarch64/h26x/sao_neon.o
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@ -39,6 +39,9 @@
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#include "alf_template.c"
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#undef BIT_DEPTH
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int ff_vvc_sad_neon(const int16_t *src0, const int16_t *src1, int dx, int dy,
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const int block_w, const int block_h);
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void ff_vvc_dsp_init_aarch64(VVCDSPContext *const c, const int bd)
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{
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int cpu_flags = av_get_cpu_flags();
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@ -125,4 +128,6 @@ void ff_vvc_dsp_init_aarch64(VVCDSPContext *const c, const int bd)
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c->alf.filter[LUMA] = alf_filter_luma_12_neon;
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c->alf.filter[CHROMA] = alf_filter_chroma_12_neon;
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}
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c->inter.sad = ff_vvc_sad_neon;
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}
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75
libavcodec/aarch64/vvc/sad.S
Normal file
75
libavcodec/aarch64/vvc/sad.S
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@ -0,0 +1,75 @@
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/*
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* Copyright (c) 2024 Zhao Zhili <quinkblack@foxmail.com>
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*
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* This file is part of FFmpeg.
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*
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* FFmpeg is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* FFmpeg is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with FFmpeg; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include "libavutil/aarch64/asm.S"
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#define VVC_MAX_PB_SIZE 128
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function ff_vvc_sad_neon, export=1
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src0 .req x0
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src1 .req x1
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dx .req w2
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dy .req w3
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block_w .req w4
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block_h .req w5
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sub w7, dx, #4
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sub w8, dy, #4
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add w6, dx, dy, lsl #7
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add w7, w7, w8, lsl #7
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sxtw x6, w6
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sxtw x7, w7
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add src0, src0, x6, lsl #1
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sub src1, src1, x7, lsl #1
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cmp block_w, #16
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movi v16.4s, #0
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b.ge 2f
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1:
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// block_w == 8
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ldr q0, [src0]
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ldr q2, [src1]
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subs block_h, block_h, #2
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sabal v16.4s, v0.4h, v2.4h
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sabal2 v16.4s, v0.8h, v2.8h
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add src0, src0, #(2 * VVC_MAX_PB_SIZE * 2)
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add src1, src1, #(2 * VVC_MAX_PB_SIZE * 2)
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b.ne 1b
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b 4f
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2:
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// block_w == 16, no block_w > 16 according the spec
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movi v17.4s, #0
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3:
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ldp q0, q1, [src0], #(2 * VVC_MAX_PB_SIZE * 2)
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ldp q2, q3, [src1], #(2 * VVC_MAX_PB_SIZE * 2)
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subs block_h, block_h, #2
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sabal v16.4s, v0.4h, v2.4h
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sabal2 v16.4s, v0.8h, v2.8h
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sabal v17.4s, v1.4h, v3.4h
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sabal2 v17.4s, v1.8h, v3.8h
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b.ne 3b
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add v16.4s, v16.4s, v17.4s
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4:
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addv s16, v16.4s
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mov w0, v16.s[0]
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ret
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endfunc
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