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avcodec/vp9: add 64-bit ipred_dr_32x32_16 avx2 implementation
vp9_diag_downright_32x32_12bpp_c: 429.7 vp9_diag_downright_32x32_12bpp_sse2: 158.9 vp9_diag_downright_32x32_12bpp_ssse3: 144.6 vp9_diag_downright_32x32_12bpp_avx: 141.0 vp9_diag_downright_32x32_12bpp_avx2: 73.8 Almost 50% faster than avx implementation Signed-off-by: Ronald S. Bultje <rsbultje@gmail.com>
This commit is contained in:
Ilia Valiakhmetov
Ronald S. Bultje
parent
0daa1cf073
commit
35a5d9715d
@ -52,8 +52,9 @@ decl_ipred_fns(dc, 16, mmxext, sse2);
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decl_ipred_fns(dc_top, 16, mmxext, sse2);
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decl_ipred_fns(dc_top, 16, mmxext, sse2);
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decl_ipred_fns(dc_left, 16, mmxext, sse2);
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decl_ipred_fns(dc_left, 16, mmxext, sse2);
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decl_ipred_fn(dl, 16, 16, avx2);
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decl_ipred_fn(dl, 16, 16, avx2);
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decl_ipred_fn(dr, 16, 16, avx2);
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decl_ipred_fn(dl, 32, 16, avx2);
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decl_ipred_fn(dl, 32, 16, avx2);
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decl_ipred_fn(dr, 16, 16, avx2);
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decl_ipred_fn(dr, 32, 16, avx2);
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#define decl_ipred_dir_funcs(type) \
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#define decl_ipred_dir_funcs(type) \
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decl_ipred_fns(type, 16, sse2, sse2); \
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decl_ipred_fns(type, 16, sse2, sse2); \
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@ -137,8 +138,9 @@ av_cold void ff_vp9dsp_init_16bpp_x86(VP9DSPContext *dsp)
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init_fpel_func(1, 1, 64, avg, _16, avx2);
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init_fpel_func(1, 1, 64, avg, _16, avx2);
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init_fpel_func(0, 1, 128, avg, _16, avx2);
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init_fpel_func(0, 1, 128, avg, _16, avx2);
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init_ipred_func(dl, DIAG_DOWN_LEFT, 16, 16, avx2);
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init_ipred_func(dl, DIAG_DOWN_LEFT, 16, 16, avx2);
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init_ipred_func(dr, DIAG_DOWN_RIGHT, 16, 16, avx2);
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init_ipred_func(dl, DIAG_DOWN_LEFT, 32, 16, avx2);
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init_ipred_func(dl, DIAG_DOWN_LEFT, 32, 16, avx2);
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init_ipred_func(dr, DIAG_DOWN_RIGHT, 16, 16, avx2);
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init_ipred_func(dr, DIAG_DOWN_RIGHT, 32, 16, avx2);
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}
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}
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#endif /* HAVE_X86ASM */
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#endif /* HAVE_X86ASM */
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@ -1221,8 +1221,109 @@ cglobal vp9_ipred_dr_16x16_16, 4, 5, 6, dst, stride, l, a
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mova [dstq+strideq*0], m4 ; 0
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mova [dstq+strideq*0], m4 ; 0
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mova [dst3q+strideq*4], m5 ; 7
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mova [dst3q+strideq*4], m5 ; 7
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RET
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RET
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%endif
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%if ARCH_X86_64
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cglobal vp9_ipred_dr_32x32_16, 4, 7, 10, dst, stride, l, a
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mova m0, [lq+mmsize*0+0] ; l[0-15]
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mova m1, [lq+mmsize*1+0] ; l[16-31]
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movu m2, [aq+mmsize*0-2] ; *abcdefghijklmno
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mova m3, [aq+mmsize*0+0] ; abcdefghijklmnop
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mova m4, [aq+mmsize*1+0] ; qrstuvwxyz012345
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vperm2i128 m5, m0, m1, q0201 ; lmnopqrstuvwxyz0
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vpalignr m6, m5, m0, 2 ; mnopqrstuvwxyz01
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vpalignr m7, m5, m0, 4 ; nopqrstuvwxyz012
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LOWPASS 0, 6, 7 ; L[0-15]
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vperm2i128 m7, m1, m2, q0201 ; stuvwxyz*abcdefg
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vpalignr m5, m7, m1, 2 ; lmnopqrstuvwxyz*
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vpalignr m6, m7, m1, 4 ; mnopqrstuvwxyz*a
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LOWPASS 1, 5, 6 ; L[16-31]#
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vperm2i128 m5, m3, m4, q0201 ; ijklmnopqrstuvwx
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vpalignr m6, m5, m3, 2 ; bcdefghijklmnopq
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LOWPASS 2, 3, 6 ; A[0-15]
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movu m3, [aq+mmsize*1-2] ; pqrstuvwxyz01234
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vperm2i128 m6, m4, m4, q2001 ; yz012345........
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vpalignr m7, m6, m4, 2 ; rstuvwxyz012345.
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LOWPASS 3, 4, 7 ; A[16-31].
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vperm2i128 m4, m1, m2, q0201 ; TUVWXYZ#ABCDEFGH
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vperm2i128 m5, m0, m1, q0201 ; L[7-15]L[16-23]
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vperm2i128 m8, m2, m3, q0201 ; IJKLMNOPQRSTUVWX
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DEFINE_ARGS dst8, stride, stride3, stride7, stride5, dst24, cnt
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lea stride3q, [strideq*3]
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lea stride5q, [stride3q+strideq*2]
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lea stride7q, [strideq*4+stride3q]
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lea dst24q, [dst8q+stride3q*8]
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lea dst8q, [dst8q+strideq*8]
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mov cntd, 2
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.loop:
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mova [dst24q+stride7q+0 ], m0 ; 31 23 15 7
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mova [dst24q+stride7q+32], m1
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mova [dst8q+stride7q+0], m1
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mova [dst8q+stride7q+32], m2
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vpalignr m6, m4, m1, 2
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vpalignr m7, m5, m0, 2
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vpalignr m9, m8, m2, 2
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mova [dst24q+stride3q*2+0], m7 ; 30 22 14 6
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mova [dst24q+stride3q*2+32], m6
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mova [dst8q+stride3q*2+0], m6
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mova [dst8q+stride3q*2+32], m9
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vpalignr m6, m4, m1, 4
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vpalignr m7, m5, m0, 4
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vpalignr m9, m8, m2, 4
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mova [dst24q+stride5q+0], m7 ; 29 21 13 5
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mova [dst24q+stride5q+32], m6
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mova [dst8q+stride5q+0], m6
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mova [dst8q+stride5q+32], m9
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vpalignr m6, m4, m1, 6
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vpalignr m7, m5, m0, 6
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vpalignr m9, m8, m2, 6
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mova [dst24q+strideq*4+0 ], m7 ; 28 20 12 4
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mova [dst24q+strideq*4+32], m6
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mova [dst8q+strideq*4+0], m6
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mova [dst8q+strideq*4+32], m9
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vpalignr m6, m4, m1, 8
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vpalignr m7, m5, m0, 8
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vpalignr m9, m8, m2, 8
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mova [dst24q+stride3q+0 ], m7 ; 27 19 11 3
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mova [dst24q+stride3q+32], m6
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mova [dst8q+stride3q+0], m6
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mova [dst8q+stride3q+32], m9
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vpalignr m6, m4, m1, 10
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vpalignr m7, m5, m0, 10
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vpalignr m9, m8, m2, 10
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mova [dst24q+strideq*2+0 ], m7 ; 26 18 10 2
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mova [dst24q+strideq*2+32], m6
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mova [dst8q+strideq*2+0], m6
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mova [dst8q+strideq*2+32], m9
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vpalignr m6, m4, m1, 12
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vpalignr m7, m5, m0, 12
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vpalignr m9, m8, m2, 12
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mova [dst24q+strideq+0 ], m7 ; 25 17 9 1
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mova [dst24q+strideq+32], m6
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mova [dst8q+strideq+0], m6
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mova [dst8q+strideq+32], m9
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vpalignr m6, m4, m1, 14
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vpalignr m7, m5, m0, 14
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vpalignr m9, m8, m2, 14
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mova [dst24q+strideq*0+0 ], m7 ; 24 16 8 0
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mova [dst24q+strideq*0+32], m6
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mova [dst8q+strideq*0+0], m6
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mova [dst8q+strideq*0+32], m9
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mova m0, m5
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mova m5, m1
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mova m1, m4
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mova m4, m2
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mova m2, m8
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mova m8, m3
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sub dst24q, stride7q
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sub dst24q, strideq
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sub dst8q, stride7q
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sub dst8q, strideq
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dec cntd
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jg .loop
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RET
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%endif
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%endif
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%macro VL_FUNCS 1 ; stack_mem_for_32x32_32bit_function
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%macro VL_FUNCS 1 ; stack_mem_for_32x32_32bit_function
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cglobal vp9_ipred_vl_4x4_16, 2, 4, 3, dst, stride, l, a
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cglobal vp9_ipred_vl_4x4_16, 2, 4, 3, dst, stride, l, a
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