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x86: vpx/h264/hevc/mpeg2: share constants
Signed-off-by: Michael Niedermayer <michaelni@gmx.at>
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@ -43,8 +43,13 @@ DECLARE_ALIGNED(16, const xmm_reg, ff_pw_64) = { 0x0040004000400040ULL, 0x004
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DECLARE_ALIGNED(8, const uint64_t, ff_pw_96) = 0x0060006000600060ULL;
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DECLARE_ALIGNED(8, const uint64_t, ff_pw_128) = 0x0080008000800080ULL;
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DECLARE_ALIGNED(8, const uint64_t, ff_pw_255) = 0x00ff00ff00ff00ffULL;
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DECLARE_ALIGNED(16, const xmm_reg, ff_pw_256) = { 0x0100010001000100ULL, 0x0100010001000100ULL };
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DECLARE_ALIGNED(16, const xmm_reg, ff_pw_512) = { 0x0200020002000200ULL, 0x0200020002000200ULL };
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DECLARE_ALIGNED(16, const xmm_reg, ff_pw_1019) = { 0x03FB03FB03FB03FBULL, 0x03FB03FB03FB03FBULL };
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DECLARE_ALIGNED(16, const xmm_reg, ff_pw_1024) = { 0x0400040004000400ULL, 0x0400040004000400ULL };
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DECLARE_ALIGNED(16, const xmm_reg, ff_pw_2048) = { 0x0800080008000800ULL, 0x0800080008000800ULL };
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DECLARE_ALIGNED(16, const xmm_reg, ff_pw_8192) = { 0x2000200020002000ULL, 0x2000200020002000ULL };
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DECLARE_ALIGNED(16, const xmm_reg, ff_pw_m1) = { 0xFFFFFFFFFFFFFFFFULL, 0xFFFFFFFFFFFFFFFFULL };
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DECLARE_ALIGNED(16, const xmm_reg, ff_pb_0) = { 0x0000000000000000ULL, 0x0000000000000000ULL };
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DECLARE_ALIGNED(32, const ymm_reg, ff_pb_1) = { 0x0101010101010101ULL, 0x0101010101010101ULL,
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@ -43,6 +43,11 @@ extern const xmm_reg ff_pw_64;
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extern const uint64_t ff_pw_96;
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extern const uint64_t ff_pw_128;
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extern const uint64_t ff_pw_255;
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extern const xmm_reg ff_pw_512;
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extern const xmm_reg ff_pw_1024;
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extern const xmm_reg ff_pw_2048;
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extern const xmm_reg ff_pw_8192;
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extern const xmm_reg ff_pw_m1;
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extern const ymm_reg ff_pb_1;
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extern const ymm_reg ff_pb_3;
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@ -26,6 +26,7 @@
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SECTION_RODATA
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cextern pw_512
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cextern pw_16
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cextern pw_8
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cextern pw_4
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@ -35,7 +36,6 @@ cextern pw_1
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pw_m32101234: dw -3, -2, -1, 0, 1, 2, 3, 4
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pw_m3: times 8 dw -3
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pw_pixel_max: times 8 dw ((1 << 10)-1)
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pw_512: times 8 dw 512
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pd_17: times 4 dd 17
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pd_16: times 4 dd 16
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@ -28,12 +28,12 @@ SECTION_RODATA
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pw_pixel_max_12: times 8 dw ((1 << 12)-1)
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pw_pixel_max_10: times 8 dw ((1 << 10)-1)
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pw_m1: times 8 dw -1
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pw_m2: times 8 dw -2
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pd_1 : times 4 dd 1
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cextern pw_4
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cextern pw_8
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cextern pw_m1
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SECTION .text
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INIT_XMM sse2
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@ -30,10 +30,11 @@
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SECTION_RODATA
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cextern pb_1
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cextern pw_2
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pw_8192: times 8 dw (1<<13)
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pb_interleave16: db 0, 8, 1, 9, 2, 10, 3, 11, 4, 12, 5, 13, 6, 14, 7, 15
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pb_interleave8: db 0, 4, 1, 5, 2, 6, 3, 7
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cextern pw_8192
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SECTION_TEXT
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; void ff_put_pixels8_x2(uint8_t *block, const uint8_t *pixels, ptrdiff_t line_size, int h)
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@ -143,13 +143,13 @@ filter_h6_shuf1: db 0, 5, 1, 6, 2, 7, 3, 8, 4, 9, 5, 10, 6, 11, 7, 12
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filter_h6_shuf2: db 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9
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filter_h6_shuf3: db 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 10, 11
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pw_256: times 8 dw 256
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pw_20091: times 4 dw 20091
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pw_17734: times 4 dw 17734
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cextern pw_3
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cextern pw_4
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cextern pw_64
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cextern pw_256
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SECTION .text
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@ -33,11 +33,7 @@ SECTION_RODATA 32
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pw_m256: times 16 dw -256
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pw_m255: times 16 dw -255
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pw_512: times 8 dw 512
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pw_1024: times 8 dw 1024
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pw_2048: times 8 dw 2048
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pw_4096: times 8 dw 4096
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pw_8192: times 8 dw 8192
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pb_4x3_4x2_4x1_4x0: times 4 db 3
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times 4 db 2
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@ -77,6 +73,10 @@ pb_15: times 16 db 15
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cextern pb_1
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cextern pb_3
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cextern pw_512
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cextern pw_1024
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cextern pw_2048
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cextern pw_8192
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SECTION .text
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@ -66,10 +66,11 @@ pw_m5283_m15212: times 4 dw -5283, -15212
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pw_13377x2: times 8 dw 13377*2
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pd_8192: times 4 dd 8192
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pw_2048: times 8 dw 2048
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pw_1024: times 8 dw 1024
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pw_512: times 8 dw 512
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pw_m1: times 8 dw -1
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cextern pw_512
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cextern pw_1024
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cextern pw_2048
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cextern pw_m1
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SECTION .text
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@ -36,8 +36,8 @@ pb_81: times 16 db 0x81
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pb_f8: times 16 db 0xf8
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pb_fe: times 16 db 0xfe
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pw_4: times 8 dw 4
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pw_8: times 8 dw 8
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cextern pw_4
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cextern pw_8
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; with mix functions, two 8-bit thresholds are stored in a 16-bit storage,
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; the following mask is used to splat both in the same register
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@ -24,8 +24,7 @@
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SECTION_RODATA
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; FIXME share with vp8dsp.asm
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pw_256: times 8 dw 256
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cextern pw_256
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%macro F8_TAPS 8
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times 8 db %1, %2
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