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checkasm: add RISC-V vector width to arch info

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Rémi Denis-Courmont 2024-11-16 09:19:46 +02:00
parent 42dd1f1cf1
commit 55aa81d5cc
1 changed files with 6 additions and 0 deletions
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6
tests/checkasm/checkasm.c
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@ -96,6 +96,8 @@
#if ARCH_AARCH64 #if ARCH_AARCH64
#include "libavutil/aarch64/cpu.h" #include "libavutil/aarch64/cpu.h"
#elif ARCH_RISCV
#include "libavutil/riscv/cpu.h"
#endif #endif
#if ARCH_ARM && HAVE_ARMV5TE_EXTERNAL #if ARCH_ARM && HAVE_ARMV5TE_EXTERNAL
@ -993,6 +995,10 @@ int main(int argc, char *argv[])
if (have_sve(av_get_cpu_flags())) if (have_sve(av_get_cpu_flags()))
snprintf(arch_info_buf, sizeof(arch_info_buf), snprintf(arch_info_buf, sizeof(arch_info_buf),
"SVE %d bits, ", 8 * ff_aarch64_sve_length()); "SVE %d bits, ", 8 * ff_aarch64_sve_length());
#elif ARCH_RISCV && HAVE_RVV
if (av_get_cpu_flags() & AV_CPU_FLAG_RVV_I32)
snprintf(arch_info_buf, sizeof (arch_info_buf),
"%zu-bit vectors, ", 8 * ff_get_rv_vlenb());
#endif #endif
fprintf(stderr, "checkasm: %susing random seed %u\n", arch_info_buf, seed); fprintf(stderr, "checkasm: %susing random seed %u\n", arch_info_buf, seed);
av_lfg_init(&checkasm_lfg, seed); av_lfg_init(&checkasm_lfg, seed);