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aarch64/vvc: Add put_qpel_hv
With Apple M1 (no i8mm): put_luma_hv_8_4x4_c: 2.2 ( 1.00x) put_luma_hv_8_4x4_neon: 0.8 ( 3.00x) put_luma_hv_8_8x8_c: 7.0 ( 1.00x) put_luma_hv_8_8x8_neon: 0.8 ( 9.33x) put_luma_hv_8_16x16_c: 22.8 ( 1.00x) put_luma_hv_8_16x16_neon: 2.5 ( 9.10x) put_luma_hv_8_32x32_c: 84.8 ( 1.00x) put_luma_hv_8_32x32_neon: 9.5 ( 8.92x) put_luma_hv_8_64x64_c: 333.0 ( 1.00x) put_luma_hv_8_64x64_neon: 35.5 ( 9.38x) put_luma_hv_8_128x128_c: 1294.5 ( 1.00x) put_luma_hv_8_128x128_neon: 137.8 ( 9.40x) With Pixel 8 Pro: put_luma_hv_8_4x4_c: 5.0 ( 1.00x) put_luma_hv_8_4x4_neon: 0.8 ( 6.67x) put_luma_hv_8_4x4_i8mm: 0.2 (20.00x) put_luma_hv_8_8x8_c: 13.2 ( 1.00x) put_luma_hv_8_8x8_neon: 1.2 (10.60x) put_luma_hv_8_8x8_i8mm: 1.2 (10.60x) put_luma_hv_8_16x16_c: 44.2 ( 1.00x) put_luma_hv_8_16x16_neon: 4.5 ( 9.83x) put_luma_hv_8_16x16_i8mm: 4.2 (10.41x) put_luma_hv_8_32x32_c: 160.8 ( 1.00x) put_luma_hv_8_32x32_neon: 17.5 ( 9.19x) put_luma_hv_8_32x32_i8mm: 16.0 (10.05x) put_luma_hv_8_64x64_c: 611.2 ( 1.00x) put_luma_hv_8_64x64_neon: 68.0 ( 8.99x) put_luma_hv_8_64x64_i8mm: 62.2 ( 9.82x) put_luma_hv_8_128x128_c: 2384.8 ( 1.00x) put_luma_hv_8_128x128_neon: 268.8 ( 8.87x) put_luma_hv_8_128x128_i8mm: 245.8 ( 9.70x)
This commit is contained in:
Zhao Zhili
Nuo Mi
parent
a0b52afd32
commit
5ac6925803
@ -282,4 +282,12 @@ void ff_vvc_put_qpel_v8_8_neon(int16_t *dst, const uint8_t *_src,
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ptrdiff_t _srcstride, int height,
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const int8_t *hf, const int8_t *vf, int width);
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NEON8_FNPROTO_PARTIAL_6(qpel_hv, (int16_t *dst,
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const uint8_t *src, ptrdiff_t srcstride, int height,
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const int8_t *hf, const int8_t *vf, int width),);
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NEON8_FNPROTO_PARTIAL_6(qpel_hv, (int16_t *dst,
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const uint8_t *src, ptrdiff_t srcstride, int height,
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const int8_t *hf, const int8_t *vf, int width), _i8mm);
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#endif
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@ -4140,9 +4140,15 @@ endfunc
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DISABLE_I8MM
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#endif
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function vvc_put_qpel_hv4_8_end_neon
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vvc_load_qpel_filterh x5
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mov x7, #(VVC_MAX_PB_SIZE * 2)
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b 1f
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endfunc
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function hevc_put_hevc_qpel_hv4_8_end_neon
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load_qpel_filterh x5, x4
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1:
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ldr d16, [sp]
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ldr d17, [sp, x7]
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add sp, sp, x7, lsl #1
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@ -4194,9 +4200,16 @@ function hevc_put_hevc_qpel_hv6_8_end_neon
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ret
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endfunc
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function vvc_put_qpel_hv8_8_end_neon
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vvc_load_qpel_filterh x5
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mov x7, #(VVC_MAX_PB_SIZE * 2)
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b 1f
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endfunc
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function hevc_put_hevc_qpel_hv8_8_end_neon
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mov x7, #128
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load_qpel_filterh x5, x4
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1:
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ldr q16, [sp]
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ldr q17, [sp, x7]
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add sp, sp, x7, lsl #1
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@ -4247,9 +4260,16 @@ function hevc_put_hevc_qpel_hv12_8_end_neon
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ret
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endfunc
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function vvc_put_qpel_hv16_8_end_neon
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vvc_load_qpel_filterh x5
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mov x7, #(VVC_MAX_PB_SIZE * 2)
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b 1f
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endfunc
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function hevc_put_hevc_qpel_hv16_8_end_neon
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mov x7, #128
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load_qpel_filterh x5, x4
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1:
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ld1 {v16.8h, v17.8h}, [sp], x7
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ld1 {v18.8h, v19.8h}, [sp], x7
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ld1 {v20.8h, v21.8h}, [sp], x7
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@ -4272,6 +4292,12 @@ function hevc_put_hevc_qpel_hv16_8_end_neon
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ret
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endfunc
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function vvc_put_qpel_hv32_8_end_neon
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vvc_load_qpel_filterh x5
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mov x7, #(VVC_MAX_PB_SIZE * 2)
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b 0f
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endfunc
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function hevc_put_hevc_qpel_hv32_8_end_neon
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mov x7, #128
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load_qpel_filterh x5, x4
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@ -4325,6 +4351,25 @@ function ff_hevc_put_hevc_qpel_hv4_8_\suffix, export=1
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b hevc_put_hevc_qpel_hv4_8_end_neon
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endfunc
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function ff_vvc_put_qpel_hv4_8_\suffix, export=1
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add w10, w3, #8
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lsl x10, x10, #8
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mov x14, sp
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sub sp, sp, x10 // tmp_array
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stp x5, x30, [sp, #-48]!
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stp x0, x3, [sp, #16]
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str x14, [sp, #32]
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add x0, sp, #48
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sub x1, x1, x2, lsl #1
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add x3, x3, #7
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sub x1, x1, x2
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bl X(ff_vvc_put_qpel_h4_8_\suffix)
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ldr x14, [sp, #32]
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ldp x0, x3, [sp, #16]
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ldp x5, x30, [sp], #48
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b vvc_put_qpel_hv4_8_end_neon
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endfunc
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function ff_hevc_put_hevc_qpel_hv6_8_\suffix, export=1
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add w10, w3, #8
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mov x7, #128
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@ -4364,6 +4409,25 @@ function ff_hevc_put_hevc_qpel_hv8_8_\suffix, export=1
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b hevc_put_hevc_qpel_hv8_8_end_neon
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endfunc
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function ff_vvc_put_qpel_hv8_8_\suffix, export=1
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add w10, w3, #8
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lsl x10, x10, #8
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sub x1, x1, x2, lsl #1
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mov x14, sp
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sub sp, sp, x10 // tmp_array
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stp x5, x30, [sp, #-48]!
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stp x0, x3, [sp, #16]
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str x14, [sp, #32]
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add x0, sp, #48
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add x3, x3, #7
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sub x1, x1, x2
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bl X(ff_vvc_put_qpel_h8_8_\suffix)
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ldr x14, [sp, #32]
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ldp x0, x3, [sp, #16]
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ldp x5, x30, [sp], #48
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b vvc_put_qpel_hv8_8_end_neon
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endfunc
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function ff_hevc_put_hevc_qpel_hv12_8_\suffix, export=1
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add w10, w3, #8
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lsl x10, x10, #7
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@ -4403,6 +4467,25 @@ function ff_hevc_put_hevc_qpel_hv16_8_\suffix, export=1
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b hevc_put_hevc_qpel_hv16_8_end_neon
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endfunc
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function ff_vvc_put_qpel_hv16_8_\suffix, export=1
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add w10, w3, #8
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lsl x10, x10, #8
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sub x1, x1, x2, lsl #1
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mov x14, sp
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sub sp, sp, x10 // tmp_array
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stp x5, x30, [sp, #-48]!
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stp x0, x3, [sp, #16]
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str x14, [sp, #32]
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add x3, x3, #7
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add x0, sp, #48
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sub x1, x1, x2
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bl X(ff_vvc_put_qpel_h16_8_\suffix)
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ldr x14, [sp, #32]
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ldp x0, x3, [sp, #16]
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ldp x5, x30, [sp], #48
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b vvc_put_qpel_hv16_8_end_neon
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endfunc
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function ff_hevc_put_hevc_qpel_hv24_8_\suffix, export=1
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stp x4, x5, [sp, #-64]!
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stp x2, x3, [sp, #16]
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@ -4439,6 +4522,26 @@ function ff_hevc_put_hevc_qpel_hv32_8_\suffix, export=1
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b hevc_put_hevc_qpel_hv32_8_end_neon
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endfunc
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function ff_vvc_put_qpel_hv32_8_\suffix, export=1
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add w10, w3, #8
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sub x1, x1, x2, lsl #1
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lsl x10, x10, #8
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sub x1, x1, x2
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mov x14, sp
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sub sp, sp, x10 // tmp_array
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stp x5, x30, [sp, #-48]!
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stp x0, x3, [sp, #16]
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str x14, [sp, #32]
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add x3, x3, #7
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add x0, sp, #48
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mov w6, #32
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bl X(ff_vvc_put_qpel_h32_8_\suffix)
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ldr x14, [sp, #32]
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ldp x0, x3, [sp, #16]
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ldp x5, x30, [sp], #48
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b vvc_put_qpel_hv32_8_end_neon
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endfunc
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function ff_hevc_put_hevc_qpel_hv48_8_\suffix, export=1
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stp x4, x5, [sp, #-64]!
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stp x2, x3, [sp, #16]
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@ -4472,6 +4575,43 @@ function ff_hevc_put_hevc_qpel_hv64_8_\suffix, export=1
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ldr x30, [sp], #16
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ret
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endfunc
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function ff_vvc_put_qpel_hv64_8_\suffix, export=1
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stp x4, x5, [sp, #-64]!
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stp x2, x3, [sp, #16]
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stp x0, x1, [sp, #32]
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str x30, [sp, #48]
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mov x6, #32
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bl X(ff_vvc_put_qpel_hv32_8_\suffix)
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ldp x0, x1, [sp, #32]
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ldp x2, x3, [sp, #16]
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ldp x4, x5, [sp], #48
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add x1, x1, #32
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add x0, x0, #64
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mov x6, #32
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bl X(ff_vvc_put_qpel_hv32_8_\suffix)
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ldr x30, [sp], #16
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ret
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endfunc
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function ff_vvc_put_qpel_hv128_8_\suffix, export=1
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stp x4, x5, [sp, #-64]!
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stp x2, x3, [sp, #16]
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stp x0, x1, [sp, #32]
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str x30, [sp, #48]
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mov x6, #64
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bl X(ff_vvc_put_qpel_hv64_8_\suffix)
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ldp x0, x1, [sp, #32]
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ldp x2, x3, [sp, #16]
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ldp x4, x5, [sp], #48
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add x1, x1, #64
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add x0, x0, #128
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mov x6, #64
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bl X(ff_vvc_put_qpel_hv64_8_\suffix)
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ldr x30, [sp], #16
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ret
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endfunc
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.endm
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qpel_hv neon
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@ -67,6 +67,13 @@ void ff_vvc_dsp_init_aarch64(VVCDSPContext *const c, const int bd)
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c->inter.put[0][5][1][0] =
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c->inter.put[0][6][1][0] = ff_vvc_put_qpel_v8_8_neon;
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c->inter.put[0][1][1][1] = ff_vvc_put_qpel_hv4_8_neon;
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c->inter.put[0][2][1][1] = ff_vvc_put_qpel_hv8_8_neon;
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c->inter.put[0][3][1][1] = ff_vvc_put_qpel_hv16_8_neon;
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c->inter.put[0][4][1][1] = ff_vvc_put_qpel_hv32_8_neon;
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c->inter.put[0][5][1][1] = ff_vvc_put_qpel_hv64_8_neon;
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c->inter.put[0][6][1][1] = ff_vvc_put_qpel_hv128_8_neon;
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c->inter.put_uni[0][1][0][0] = ff_vvc_put_pel_uni_pixels4_8_neon;
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c->inter.put_uni[0][2][0][0] = ff_vvc_put_pel_uni_pixels8_8_neon;
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c->inter.put_uni[0][3][0][0] = ff_vvc_put_pel_uni_pixels16_8_neon;
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@ -103,6 +110,13 @@ void ff_vvc_dsp_init_aarch64(VVCDSPContext *const c, const int bd)
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c->inter.put[0][4][0][1] = ff_vvc_put_qpel_h32_8_neon_i8mm;
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c->inter.put[0][5][0][1] = ff_vvc_put_qpel_h64_8_neon_i8mm;
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c->inter.put[0][6][0][1] = ff_vvc_put_qpel_h128_8_neon_i8mm;
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c->inter.put[0][1][1][1] = ff_vvc_put_qpel_hv4_8_neon_i8mm;
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c->inter.put[0][2][1][1] = ff_vvc_put_qpel_hv8_8_neon_i8mm;
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c->inter.put[0][3][1][1] = ff_vvc_put_qpel_hv16_8_neon_i8mm;
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c->inter.put[0][4][1][1] = ff_vvc_put_qpel_hv32_8_neon_i8mm;
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c->inter.put[0][5][1][1] = ff_vvc_put_qpel_hv64_8_neon_i8mm;
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c->inter.put[0][6][1][1] = ff_vvc_put_qpel_hv128_8_neon_i8mm;
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}
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} else if (bd == 10) {
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c->alf.filter[LUMA] = alf_filter_luma_10_neon;
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