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mips: fix build fail on MIPS R6

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Add macro define to avoid causing build fail with incompatible assembler code on MIPS R6.

Signed-off-by: Junxian Zhu <zhujunxian@oss.cipunited.com>
Reviewed-by: Shiyou Yin <yinshiyou-hf@loongson.cn>
Signed-off-by: Michael Niedermayer <michael@niedermayer.cc>
This commit is contained in:
Junxian Zhu
2022-12-01 15:00:06 +08:00
committed by Michael Niedermayer
parent 653ee3f159
commit 5ffe18bcea
3 changed files with 7 additions and 3 deletions
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2
libavcodec/mips/cabac.h
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@@ -30,6 +30,7 @@
#include "libavutil/mips/mmiutils.h" #include "libavutil/mips/mmiutils.h"
#include "config.h" #include "config.h"
#if !HAVE_MIPS32R6 && !HAVE_MIPS64R6
#define get_cabac_inline get_cabac_inline_mips #define get_cabac_inline get_cabac_inline_mips
static av_always_inline int get_cabac_inline_mips(CABACContext *c, static av_always_inline int get_cabac_inline_mips(CABACContext *c,
uint8_t * const state){ uint8_t * const state){
@@ -225,4 +226,5 @@ static av_always_inline int get_cabac_bypass_sign_mips(CABACContext *c, int val)
return res; return res;
} }
#endif /* !HAVE_MIPS32R6 && !HAVE_MIPS64R6 */
#endif /* AVCODEC_MIPS_CABAC_H */ #endif /* AVCODEC_MIPS_CABAC_H */

2
libavcodec/mips/compute_antialias_fixed.h
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@@ -56,6 +56,7 @@
#define AVCODEC_MIPS_COMPUTE_ANTIALIAS_FIXED_H #define AVCODEC_MIPS_COMPUTE_ANTIALIAS_FIXED_H
#if HAVE_INLINE_ASM #if HAVE_INLINE_ASM
#if !HAVE_MIPS32R6 && !HAVE_MIPS64R6
static void compute_antialias_mips_fixed(MPADecodeContext *s, static void compute_antialias_mips_fixed(MPADecodeContext *s,
GranuleDef *g) GranuleDef *g)
{ {
@@ -246,6 +247,7 @@ static void compute_antialias_mips_fixed(MPADecodeContext *s,
} }
} }
#define compute_antialias compute_antialias_mips_fixed #define compute_antialias compute_antialias_mips_fixed
#endif /* !HAVE_MIPS32R6 && !HAVE_MIPS64R6 */
#endif /* HAVE_INLINE_ASM */ #endif /* HAVE_INLINE_ASM */
#endif /* AVCODEC_MIPS_COMPUTE_ANTIALIAS_FIXED_H */ #endif /* AVCODEC_MIPS_COMPUTE_ANTIALIAS_FIXED_H */

6
libavutil/mips/generic_macros_msa.h
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@@ -44,7 +44,7 @@
#define ST_UW(...) ST_V(v4u32, __VA_ARGS__) #define ST_UW(...) ST_V(v4u32, __VA_ARGS__)
#define ST_SW(...) ST_V(v4i32, __VA_ARGS__) #define ST_SW(...) ST_V(v4i32, __VA_ARGS__)
#if (__mips_isa_rev >= 6) #if HAVE_MIPS32R6 || HAVE_MIPS64R6
#define LH(psrc) \ #define LH(psrc) \
( { \ ( { \
uint16_t val_lh_m = *(uint16_t *)(psrc); \ uint16_t val_lh_m = *(uint16_t *)(psrc); \
@@ -85,7 +85,7 @@
#define SW(val, pdst) *(uint32_t *)(pdst) = (val); #define SW(val, pdst) *(uint32_t *)(pdst) = (val);
#define SD(val, pdst) *(uint64_t *)(pdst) = (val); #define SD(val, pdst) *(uint64_t *)(pdst) = (val);
#else // !(__mips_isa_rev >= 6) #else // !HAVE_MIPS32R6 && !HAVE_MIPS64R6
#define LH(psrc) \ #define LH(psrc) \
( { \ ( { \
uint8_t *psrc_lh_m = (uint8_t *) (psrc); \ uint8_t *psrc_lh_m = (uint8_t *) (psrc); \
@@ -188,7 +188,7 @@
SW(val0_sd_m, pdst_sd_m); \ SW(val0_sd_m, pdst_sd_m); \
SW(val1_sd_m, pdst_sd_m + 4); \ SW(val1_sd_m, pdst_sd_m + 4); \
} }
#endif // (__mips_isa_rev >= 6) #endif // HAVE_MIPS32R6 || HAVE_MIPS64R6
/* Description : Load 4 words with stride /* Description : Load 4 words with stride
Arguments : Inputs - psrc (source pointer to load from) Arguments : Inputs - psrc (source pointer to load from)