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avcodec/vc1: Arm 64-bit NEON unescape fast path
checkasm benchmarks on 1.5 GHz Cortex-A72 are as follows. vc1dsp.vc1_unescape_buffer_c: 655617.7 vc1dsp.vc1_unescape_buffer_neon: 118237.0 Signed-off-by: Ben Avison <bavison@riscosopen.org> Signed-off-by: Martin Storsjö <martin@martin.st>
This commit is contained in:
Ben Avison
committed by
Martin Storsjö
Martin Storsjö
parent
5379412ed0
commit
6eee650289
@@ -21,6 +21,7 @@
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#include "libavutil/attributes.h"
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#include "libavutil/attributes.h"
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#include "libavutil/cpu.h"
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#include "libavutil/cpu.h"
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#include "libavutil/aarch64/cpu.h"
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#include "libavutil/aarch64/cpu.h"
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#include "libavutil/intreadwrite.h"
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#include "libavcodec/vc1dsp.h"
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#include "libavcodec/vc1dsp.h"
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#include "config.h"
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#include "config.h"
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@@ -51,6 +52,64 @@ void ff_put_vc1_chroma_mc4_neon(uint8_t *dst, uint8_t *src, ptrdiff_t stride,
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void ff_avg_vc1_chroma_mc4_neon(uint8_t *dst, uint8_t *src, ptrdiff_t stride,
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void ff_avg_vc1_chroma_mc4_neon(uint8_t *dst, uint8_t *src, ptrdiff_t stride,
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int h, int x, int y);
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int h, int x, int y);
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int ff_vc1_unescape_buffer_helper_neon(const uint8_t *src, int size, uint8_t *dst);
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static int vc1_unescape_buffer_neon(const uint8_t *src, int size, uint8_t *dst)
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{
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/* Dealing with starting and stopping, and removing escape bytes, are
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* comparatively less time-sensitive, so are more clearly expressed using
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* a C wrapper around the assembly inner loop. Note that we assume a
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* little-endian machine that supports unaligned loads. */
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int dsize = 0;
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while (size >= 4)
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{
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int found = 0;
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while (!found && (((uintptr_t) dst) & 7) && size >= 4)
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{
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found = (AV_RL32(src) &~ 0x03000000) == 0x00030000;
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if (!found)
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{
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*dst++ = *src++;
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--size;
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++dsize;
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}
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}
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if (!found)
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{
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int skip = size - ff_vc1_unescape_buffer_helper_neon(src, size, dst);
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dst += skip;
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src += skip;
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size -= skip;
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dsize += skip;
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while (!found && size >= 4)
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{
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found = (AV_RL32(src) &~ 0x03000000) == 0x00030000;
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if (!found)
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{
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*dst++ = *src++;
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--size;
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++dsize;
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}
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}
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}
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if (found)
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{
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*dst++ = *src++;
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*dst++ = *src++;
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++src;
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size -= 3;
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dsize += 2;
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}
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}
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while (size > 0)
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{
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*dst++ = *src++;
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--size;
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++dsize;
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}
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return dsize;
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}
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av_cold void ff_vc1dsp_init_aarch64(VC1DSPContext *dsp)
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av_cold void ff_vc1dsp_init_aarch64(VC1DSPContext *dsp)
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{
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{
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int cpu_flags = av_get_cpu_flags();
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int cpu_flags = av_get_cpu_flags();
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@@ -76,5 +135,7 @@ av_cold void ff_vc1dsp_init_aarch64(VC1DSPContext *dsp)
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dsp->avg_no_rnd_vc1_chroma_pixels_tab[0] = ff_avg_vc1_chroma_mc8_neon;
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dsp->avg_no_rnd_vc1_chroma_pixels_tab[0] = ff_avg_vc1_chroma_mc8_neon;
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dsp->put_no_rnd_vc1_chroma_pixels_tab[1] = ff_put_vc1_chroma_mc4_neon;
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dsp->put_no_rnd_vc1_chroma_pixels_tab[1] = ff_put_vc1_chroma_mc4_neon;
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dsp->avg_no_rnd_vc1_chroma_pixels_tab[1] = ff_avg_vc1_chroma_mc4_neon;
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dsp->avg_no_rnd_vc1_chroma_pixels_tab[1] = ff_avg_vc1_chroma_mc4_neon;
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dsp->vc1_unescape_buffer = vc1_unescape_buffer_neon;
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}
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}
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}
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}
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@@ -1368,3 +1368,179 @@ function ff_vc1_h_loop_filter16_neon, export=1
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st2 {v2.b, v3.b}[7], [x6]
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st2 {v2.b, v3.b}[7], [x6]
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4: ret
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4: ret
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endfunc
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endfunc
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// Copy at most the specified number of bytes from source to destination buffer,
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// stopping at a multiple of 32 bytes, none of which are the start of an escape sequence
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// On entry:
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// x0 -> source buffer
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// w1 = max number of bytes to copy
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// x2 -> destination buffer, optimally 8-byte aligned
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// On exit:
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// w0 = number of bytes not copied
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function ff_vc1_unescape_buffer_helper_neon, export=1
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// Offset by 80 to screen out cases that are too short for us to handle,
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// and also make it easy to test for loop termination, or to determine
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// whether we need an odd number of half-iterations of the loop.
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subs w1, w1, #80
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b.mi 90f
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// Set up useful constants
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movi v20.4s, #3, lsl #24
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movi v21.4s, #3, lsl #16
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tst w1, #32
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b.ne 1f
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ld1 {v0.16b, v1.16b, v2.16b}, [x0], #48
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ext v25.16b, v0.16b, v1.16b, #1
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ext v26.16b, v0.16b, v1.16b, #2
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ext v27.16b, v0.16b, v1.16b, #3
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ext v29.16b, v1.16b, v2.16b, #1
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ext v30.16b, v1.16b, v2.16b, #2
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ext v31.16b, v1.16b, v2.16b, #3
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bic v24.16b, v0.16b, v20.16b
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bic v25.16b, v25.16b, v20.16b
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bic v26.16b, v26.16b, v20.16b
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bic v27.16b, v27.16b, v20.16b
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bic v28.16b, v1.16b, v20.16b
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bic v29.16b, v29.16b, v20.16b
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bic v30.16b, v30.16b, v20.16b
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bic v31.16b, v31.16b, v20.16b
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eor v24.16b, v24.16b, v21.16b
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eor v25.16b, v25.16b, v21.16b
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eor v26.16b, v26.16b, v21.16b
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eor v27.16b, v27.16b, v21.16b
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eor v28.16b, v28.16b, v21.16b
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eor v29.16b, v29.16b, v21.16b
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eor v30.16b, v30.16b, v21.16b
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eor v31.16b, v31.16b, v21.16b
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cmeq v24.4s, v24.4s, #0
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cmeq v25.4s, v25.4s, #0
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cmeq v26.4s, v26.4s, #0
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cmeq v27.4s, v27.4s, #0
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add w1, w1, #32
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b 3f
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1: ld1 {v3.16b, v4.16b, v5.16b}, [x0], #48
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ext v25.16b, v3.16b, v4.16b, #1
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ext v26.16b, v3.16b, v4.16b, #2
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ext v27.16b, v3.16b, v4.16b, #3
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ext v29.16b, v4.16b, v5.16b, #1
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ext v30.16b, v4.16b, v5.16b, #2
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ext v31.16b, v4.16b, v5.16b, #3
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bic v24.16b, v3.16b, v20.16b
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bic v25.16b, v25.16b, v20.16b
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bic v26.16b, v26.16b, v20.16b
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bic v27.16b, v27.16b, v20.16b
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bic v28.16b, v4.16b, v20.16b
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bic v29.16b, v29.16b, v20.16b
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bic v30.16b, v30.16b, v20.16b
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bic v31.16b, v31.16b, v20.16b
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eor v24.16b, v24.16b, v21.16b
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eor v25.16b, v25.16b, v21.16b
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eor v26.16b, v26.16b, v21.16b
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eor v27.16b, v27.16b, v21.16b
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eor v28.16b, v28.16b, v21.16b
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eor v29.16b, v29.16b, v21.16b
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eor v30.16b, v30.16b, v21.16b
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eor v31.16b, v31.16b, v21.16b
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cmeq v24.4s, v24.4s, #0
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cmeq v25.4s, v25.4s, #0
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cmeq v26.4s, v26.4s, #0
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cmeq v27.4s, v27.4s, #0
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// Drop through...
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2: mov v0.16b, v5.16b
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ld1 {v1.16b, v2.16b}, [x0], #32
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cmeq v28.4s, v28.4s, #0
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cmeq v29.4s, v29.4s, #0
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cmeq v30.4s, v30.4s, #0
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cmeq v31.4s, v31.4s, #0
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orr v24.16b, v24.16b, v25.16b
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orr v26.16b, v26.16b, v27.16b
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orr v28.16b, v28.16b, v29.16b
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orr v30.16b, v30.16b, v31.16b
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ext v25.16b, v0.16b, v1.16b, #1
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orr v22.16b, v24.16b, v26.16b
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ext v26.16b, v0.16b, v1.16b, #2
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ext v27.16b, v0.16b, v1.16b, #3
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ext v29.16b, v1.16b, v2.16b, #1
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orr v23.16b, v28.16b, v30.16b
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ext v30.16b, v1.16b, v2.16b, #2
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ext v31.16b, v1.16b, v2.16b, #3
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bic v24.16b, v0.16b, v20.16b
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bic v25.16b, v25.16b, v20.16b
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bic v26.16b, v26.16b, v20.16b
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orr v22.16b, v22.16b, v23.16b
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bic v27.16b, v27.16b, v20.16b
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bic v28.16b, v1.16b, v20.16b
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bic v29.16b, v29.16b, v20.16b
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bic v30.16b, v30.16b, v20.16b
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bic v31.16b, v31.16b, v20.16b
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addv s22, v22.4s
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eor v24.16b, v24.16b, v21.16b
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eor v25.16b, v25.16b, v21.16b
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eor v26.16b, v26.16b, v21.16b
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eor v27.16b, v27.16b, v21.16b
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eor v28.16b, v28.16b, v21.16b
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mov w3, v22.s[0]
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eor v29.16b, v29.16b, v21.16b
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eor v30.16b, v30.16b, v21.16b
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eor v31.16b, v31.16b, v21.16b
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cmeq v24.4s, v24.4s, #0
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cmeq v25.4s, v25.4s, #0
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cmeq v26.4s, v26.4s, #0
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cmeq v27.4s, v27.4s, #0
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cbnz w3, 90f
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st1 {v3.16b, v4.16b}, [x2], #32
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3: mov v3.16b, v2.16b
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ld1 {v4.16b, v5.16b}, [x0], #32
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cmeq v28.4s, v28.4s, #0
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cmeq v29.4s, v29.4s, #0
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cmeq v30.4s, v30.4s, #0
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cmeq v31.4s, v31.4s, #0
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orr v24.16b, v24.16b, v25.16b
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orr v26.16b, v26.16b, v27.16b
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orr v28.16b, v28.16b, v29.16b
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orr v30.16b, v30.16b, v31.16b
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ext v25.16b, v3.16b, v4.16b, #1
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orr v22.16b, v24.16b, v26.16b
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ext v26.16b, v3.16b, v4.16b, #2
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ext v27.16b, v3.16b, v4.16b, #3
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ext v29.16b, v4.16b, v5.16b, #1
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orr v23.16b, v28.16b, v30.16b
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ext v30.16b, v4.16b, v5.16b, #2
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ext v31.16b, v4.16b, v5.16b, #3
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bic v24.16b, v3.16b, v20.16b
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bic v25.16b, v25.16b, v20.16b
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bic v26.16b, v26.16b, v20.16b
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orr v22.16b, v22.16b, v23.16b
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bic v27.16b, v27.16b, v20.16b
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bic v28.16b, v4.16b, v20.16b
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bic v29.16b, v29.16b, v20.16b
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bic v30.16b, v30.16b, v20.16b
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bic v31.16b, v31.16b, v20.16b
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addv s22, v22.4s
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eor v24.16b, v24.16b, v21.16b
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eor v25.16b, v25.16b, v21.16b
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eor v26.16b, v26.16b, v21.16b
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eor v27.16b, v27.16b, v21.16b
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eor v28.16b, v28.16b, v21.16b
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mov w3, v22.s[0]
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eor v29.16b, v29.16b, v21.16b
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eor v30.16b, v30.16b, v21.16b
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eor v31.16b, v31.16b, v21.16b
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cmeq v24.4s, v24.4s, #0
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cmeq v25.4s, v25.4s, #0
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cmeq v26.4s, v26.4s, #0
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cmeq v27.4s, v27.4s, #0
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cbnz w3, 91f
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st1 {v0.16b, v1.16b}, [x2], #32
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subs w1, w1, #64
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b.pl 2b
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90: add w0, w1, #80
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ret
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91: sub w1, w1, #32
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b 90b
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endfunc
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