virtualenv/FFmpeg
1
0
Fork 0
mirror of https://github.com/FFmpeg/FFmpeg.git synced 2025-10-30 23:18:11 +02:00
Code Issues Releases Activity

sws/rgb2rgb: RISC-V V interleaveBytes

Browse Source
This commit is contained in:
Rémi Denis-Courmont
2022-09-28 18:30:00 +03:00
committed by Lynne
parent 66a03f4053
commit 9181835a24
2 changed files with 30 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
libswscale/riscv/rgb2rgb.c
View File

@@ -30,6 +30,9 @@ void ff_shuffle_bytes_2103_rvv(const uint8_t *src, uint8_t *dst, int src_len);
void ff_shuffle_bytes_1230_rvv(const uint8_t *src, uint8_t *dst, int src_len); void ff_shuffle_bytes_1230_rvv(const uint8_t *src, uint8_t *dst, int src_len);
void ff_shuffle_bytes_3012_rvv(const uint8_t *src, uint8_t *dst, int src_len); void ff_shuffle_bytes_3012_rvv(const uint8_t *src, uint8_t *dst, int src_len);
void ff_shuffle_bytes_3210_rvv(const uint8_t *src, uint8_t *dst, int src_len); void ff_shuffle_bytes_3210_rvv(const uint8_t *src, uint8_t *dst, int src_len);
void ff_interleave_bytes_rvv(const uint8_t *src1, const uint8_t *src2,
uint8_t *dst, int width, int height, int s1stride,
int s2stride, int dstride);
av_cold void rgb2rgb_init_riscv(void) av_cold void rgb2rgb_init_riscv(void)
{ {
@@ -42,6 +45,7 @@ av_cold void rgb2rgb_init_riscv(void)
shuffle_bytes_1230 = ff_shuffle_bytes_1230_rvv; shuffle_bytes_1230 = ff_shuffle_bytes_1230_rvv;
shuffle_bytes_3012 = ff_shuffle_bytes_3012_rvv; shuffle_bytes_3012 = ff_shuffle_bytes_3012_rvv;
shuffle_bytes_3210 = ff_shuffle_bytes_3210_rvv; shuffle_bytes_3210 = ff_shuffle_bytes_3210_rvv;
interleaveBytes = ff_interleave_bytes_rvv;
} }
#endif #endif
} }

26
libswscale/riscv/rgb2rgb_rvv.S
View File

@@ -76,3 +76,29 @@ func ff_shuffle_bytes_3210_rvv, zve32x
addi a0, a0, 3 addi a0, a0, 3
j 1b j 1b
endfunc endfunc
func ff_interleave_bytes_rvv, zve32x
1:
mv t0, a0
mv t1, a1
mv t2, a2
mv t3, a3
addi a4, a4, -1
2:
vsetvli t4, t3, e8, ta, ma
sub t3, t3, t4
vle8.v v8, (t0)
add t0, t4, t0
vle8.v v9, (t1)
add t1, t4, t1
vsseg2e8.v v8, (t2)
sh1add t2, t4, t2
bnez t4, 2b
add a0, a0, a5
add a1, a1, a6
add a2, a2, a7
bnez a4, 1b
ret
endfunc