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x86: cpu: whitespace (mostly) cosmetics

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This adds whitespace around operators, aligns line continuation
backslashes, and breaks long lines.  Also fixes an ifdef halfway
through a statement.  The one line of duplication this saved is
not worth the ugliness.

Signed-off-by: Mans Rullgard <mans@mansr.com>
This commit is contained in:
Mans Rullgard
2012-06-25 13:43:32 +01:00
parent 8725da49a2
commit 963cdf39b4
1 changed files with 35 additions and 33 deletions
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34
libavutil/x86/cpu.c
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@@ -27,13 +27,12 @@
/* ebx saving is necessary for PIC. gcc seems unable to see it alone */
#define cpuid(index, eax, ebx, ecx, edx) \
__asm__ volatile\
("mov %%"REG_b", %%"REG_S"\n\t"\
__asm__ volatile ( \
"mov %%"REG_b", %%"REG_S" \n\t" \
"cpuid \n\t" \
"xchg %%"REG_b", %%"REG_S \
: "=a" (eax), "=S" (ebx),\
"=c" (ecx), "=d" (edx)\
: "0" (index));
: "=a" (eax), "=S" (ebx), "=c" (ecx), "=d" (edx) \
: "0" (index))
#define xgetbv(index, eax, edx) \
__asm__ (".byte 0x0f, 0x01, 0xd0" : "=a"(eax), "=d"(edx) : "c" (index))
@@ -88,9 +87,10 @@ int ff_get_cpu_flags_x86(void)
if (std_caps & (1 << 23))
rval |= AV_CPU_FLAG_MMX;
if (std_caps & (1 << 25))
rval |= AV_CPU_FLAG_MMX2
rval |= AV_CPU_FLAG_MMX2;
#if HAVE_SSE
| AV_CPU_FLAG_SSE;
if (std_caps & (1 << 25))
rval |= AV_CPU_FLAG_SSE;
if (std_caps & (1 << 26))
rval |= AV_CPU_FLAG_SSE2;
if (ecx & 1)
@@ -111,7 +111,6 @@ int ff_get_cpu_flags_x86(void)
}
#endif
#endif
;
}
cpuid(0x80000000, max_ext_level, ebx, ecx, edx);
@@ -151,14 +150,17 @@ int ff_get_cpu_flags_x86(void)
if (!strncmp(vendor.c, "GenuineIntel", 12)) {
if (family == 6 && (model == 9 || model == 13 || model == 14)) {
/* 6/9 (pentium-m "banias"), 6/13 (pentium-m "dothan"), and 6/14 (core1 "yonah")
* theoretically support sse2, but it's usually slower than mmx,
* so let's just pretend they don't. AV_CPU_FLAG_SSE2 is disabled and
* AV_CPU_FLAG_SSE2SLOW is enabled so that SSE2 is not used unless
* explicitly enabled by checking AV_CPU_FLAG_SSE2SLOW. The same
* situation applies for AV_CPU_FLAG_SSE3 and AV_CPU_FLAG_SSE3SLOW. */
if (rval & AV_CPU_FLAG_SSE2) rval ^= AV_CPU_FLAG_SSE2SLOW|AV_CPU_FLAG_SSE2;
if (rval & AV_CPU_FLAG_SSE3) rval ^= AV_CPU_FLAG_SSE3SLOW|AV_CPU_FLAG_SSE3;
/* 6/9 (pentium-m "banias"), 6/13 (pentium-m "dothan"), and
* 6/14 (core1 "yonah") theoretically support sse2, but it's
* usually slower than mmx, so let's just pretend they don't.
* AV_CPU_FLAG_SSE2 is disabled and AV_CPU_FLAG_SSE2SLOW is
* enabled so that SSE2 is not used unless explicitly enabled
* by checking AV_CPU_FLAG_SSE2SLOW. The same situation
* applies for AV_CPU_FLAG_SSE3 and AV_CPU_FLAG_SSE3SLOW. */
if (rval & AV_CPU_FLAG_SSE2)
rval ^= AV_CPU_FLAG_SSE2SLOW | AV_CPU_FLAG_SSE2;
if (rval & AV_CPU_FLAG_SSE3)
rval ^= AV_CPU_FLAG_SSE3SLOW | AV_CPU_FLAG_SSE3;
}
/* The Atom processor has SSSE3 support, which is useful in many cases,
* but sometimes the SSSE3 version is slower than the SSE2 equivalent