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Code Issues Releases Activity

Fix the tail handling in R-V V sad

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Signed-off-by: Rémi Denis-Courmont <remi@remlab.net>
This commit is contained in:
sunyuechi
2024-12-23 23:01:32 +08:00
committed by Rémi Denis-Courmont
parent e20ee9f9ae
commit a0a89efd07
2 changed files with 19 additions and 19 deletions
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36
libavcodec/riscv/h26x/asm.S
View File

@@ -20,46 +20,46 @@
#include "libavutil/riscv/asm.S" #include "libavutil/riscv/asm.S"
.macro vsetvlstatic w, vlen, en, mn1, mn2, mn3, mn4, mn5, mn6 .macro vsetvlstatic w, vlen, en, mn1, mn2, mn3, mn4, mn5, mn6, vta=ta
.if \w == 2 && \vlen == 128 .if \w == 2 && \vlen == 128
vsetivli zero, \w, \en, \mn1, ta, ma vsetivli zero, \w, \en, \mn1, \vta, ma
.elseif \w <= 4 && \vlen == 128 .elseif \w <= 4 && \vlen == 128
vsetivli zero, \w, \en, \mn2, ta, ma vsetivli zero, \w, \en, \mn2, \vta, ma
.elseif \w <= 8 && \vlen == 128 .elseif \w <= 8 && \vlen == 128
vsetivli zero, \w, \en, \mn3, ta, ma vsetivli zero, \w, \en, \mn3, \vta, ma
.elseif \w <= 16 && \vlen == 128 .elseif \w <= 16 && \vlen == 128
vsetivli zero, \w, \en, \mn4, ta, ma vsetivli zero, \w, \en, \mn4, \vta, ma
.elseif \w <= 32 && \vlen == 128 .elseif \w <= 32 && \vlen == 128
li t0, \w li t0, \w
vsetvli zero, t0, \en, \mn5, ta, ma vsetvli zero, t0, \en, \mn5, \vta, ma
.elseif \w <= 4 && \vlen == 256 .elseif \w <= 4 && \vlen == 256
vsetivli zero, \w, \en, \mn1, ta, ma vsetivli zero, \w, \en, \mn1, \vta, ma
.elseif \w <= 8 && \vlen == 256 .elseif \w <= 8 && \vlen == 256
vsetivli zero, \w, \en, \mn2, ta, ma vsetivli zero, \w, \en, \mn2, \vta, ma
.elseif \w <= 16 && \vlen == 256 .elseif \w <= 16 && \vlen == 256
vsetivli zero, \w, \en, \mn3, ta, ma vsetivli zero, \w, \en, \mn3, \vta, ma
.elseif \w <= 32 && \vlen == 256 .elseif \w <= 32 && \vlen == 256
li t0, \w li t0, \w
vsetvli zero, t0, \en, \mn4, ta, ma vsetvli zero, t0, \en, \mn4, \vta, ma
.elseif \w <= 64 && \vlen == 256 .elseif \w <= 64 && \vlen == 256
li t0, \w li t0, \w
vsetvli zero, t0, \en, \mn5, ta, ma vsetvli zero, t0, \en, \mn5, \vta, ma
.else .else
li t0, \w li t0, \w
vsetvli zero, t0, \en, \mn6, ta, ma vsetvli zero, t0, \en, \mn6, \vta, ma
.endif .endif
.endm .endm
.macro vsetvlstatic8 w, vlen .macro vsetvlstatic8 w, vlen, vta
vsetvlstatic \w, \vlen, e8, mf8, mf4, mf2, m1, m2, m4 vsetvlstatic \w, \vlen, e8, mf8, mf4, mf2, m1, m2, m4, \vta
.endm .endm
.macro vsetvlstatic16 w, vlen .macro vsetvlstatic16 w, vlen, vta
vsetvlstatic \w, \vlen, e16, mf4, mf2, m1, m2, m4, m8 vsetvlstatic \w, \vlen, e16, mf4, mf2, m1, m2, m4, m8, \vta
.endm .endm
.macro vsetvlstatic32 w, vlen .macro vsetvlstatic32 w, vlen, vta
vsetvlstatic \w, \vlen, e32, mf2, m1, m2, m4, m8, m8 vsetvlstatic \w, \vlen, e32, mf2, m1, m2, m4, m8, m8, \vta
.endm .endm
.macro POW2_JMP_TABLE id, vlen .macro POW2_JMP_TABLE id, vlen

2
libavcodec/riscv/vvc/sad_rvv.S
View File

@@ -37,7 +37,7 @@ SADVSET\vlen\w:
vsetvlstatic32 \w, \vlen vsetvlstatic32 \w, \vlen
vmv.v.i v0, 0 vmv.v.i v0, 0
vmv.s.x v24, zero vmv.s.x v24, zero
vsetvlstatic16 \w, \vlen vsetvlstatic16 \w, \vlen, tu
SAD\vlen\w: SAD\vlen\w:
addi a5, a5, -2 addi a5, a5, -2
vle16.v v8, (a0) vle16.v v8, (a0)