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Code Issues Releases Activity

lavc/flacdsp: fix CPU requirement for 32-bit LPC

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This commit is contained in:
Rémi Denis-Courmont 2024-05-13 18:51:38 +03:00
parent 8670615743
commit a3e45063c0
2 changed files with 5 additions and 3 deletions

4
libavcodec/riscv/flacdsp_init.c

@ -69,9 +69,11 @@ av_cold void ff_flacdsp_init_riscv(FLACDSPContext *c, enum AVSampleFormat fmt,
if ((flags & AV_CPU_FLAG_RVV_I32) && (flags & AV_CPU_FLAG_RVB_ADDR)) {
int vlenb = ff_get_rv_vlenb();
if (vlenb >= 16) {
if (vlenb >= 16)
c->lpc16 = ff_flac_lpc16_rvv;
# if (__riscv_xlen >= 64)
if (flags & AV_CPU_FLAG_RVV_I64) {
if (vlenb > 16)
c->lpc32 = ff_flac_lpc32_rvv_simple;
else

4
libavcodec/riscv/flacdsp_rvv.S

@ -44,7 +44,7 @@ func ff_flac_lpc16_rvv, zve32x
endfunc
#if (__riscv_xlen == 64)
func ff_flac_lpc32_rvv, zve32x
func ff_flac_lpc32_rvv, zve64x
addi t2, a2, -16
ble t2, zero, ff_flac_lpc32_rvv_simple
vsetivli zero, 1, e64, m1, ta, ma
@ -75,7 +75,7 @@ func ff_flac_lpc32_rvv, zve32x
ret
endfunc
func ff_flac_lpc32_rvv_simple, zve32x
func ff_flac_lpc32_rvv_simple, zve64x
vsetivli zero, 1, e64, m1, ta, ma
vmv.s.x v0, zero
vsetvli zero, a2, e32, m4, ta, ma