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port ape dsp functions from sse2 to mmx
now requires yasm Originally committed as revision 20722 to svn://svn.ffmpeg.org/ffmpeg/trunk
This commit is contained in:
Loren Merritt
parent
f415be684d
commit
b10fa1bb8b
@ -2384,6 +2384,12 @@ static void float_to_int16_sse2(int16_t *dst, const float *src, long len){
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void ff_float_to_int16_interleave6_sse(int16_t *dst, const float **src, int len);
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void ff_float_to_int16_interleave6_3dnow(int16_t *dst, const float **src, int len);
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void ff_float_to_int16_interleave6_3dn2(int16_t *dst, const float **src, int len);
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void ff_add_int16_mmx2(int16_t * v1, int16_t * v2, int order);
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void ff_add_int16_sse2(int16_t * v1, int16_t * v2, int order);
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void ff_sub_int16_mmx2(int16_t * v1, int16_t * v2, int order);
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void ff_sub_int16_sse2(int16_t * v1, int16_t * v2, int order);
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int32_t ff_scalarproduct_int16_mmx2(int16_t * v1, int16_t * v2, int order, int shift);
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int32_t ff_scalarproduct_int16_sse2(int16_t * v1, int16_t * v2, int order, int shift);
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void ff_add_hfyu_median_prediction_mmx2(uint8_t *dst, const uint8_t *top, const uint8_t *diff, int w, int *left, int *left_top);
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int ff_add_hfyu_left_prediction_ssse3(uint8_t *dst, const uint8_t *src, int w, int left);
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int ff_add_hfyu_left_prediction_sse4(uint8_t *dst, const uint8_t *src, int w, int left);
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@ -2507,78 +2513,6 @@ void ff_snow_inner_add_yblock_mmx(const uint8_t *obmc, const int obmc_stride, ui
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int src_x, int src_y, int src_stride, slice_buffer * sb, int add, uint8_t * dst8);
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static void add_int16_sse2(int16_t * v1, int16_t * v2, int order)
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{
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x86_reg o = -(order << 1);
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v1 += order;
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v2 += order;
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__asm__ volatile(
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"1: \n\t"
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"movdqu (%1,%2), %%xmm0 \n\t"
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"movdqu 16(%1,%2), %%xmm1 \n\t"
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"paddw (%0,%2), %%xmm0 \n\t"
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"paddw 16(%0,%2), %%xmm1 \n\t"
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"movdqa %%xmm0, (%0,%2) \n\t"
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"movdqa %%xmm1, 16(%0,%2) \n\t"
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"add $32, %2 \n\t"
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"js 1b \n\t"
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: "+r"(v1), "+r"(v2), "+r"(o)
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);
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}
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static void sub_int16_sse2(int16_t * v1, int16_t * v2, int order)
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{
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x86_reg o = -(order << 1);
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v1 += order;
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v2 += order;
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__asm__ volatile(
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"1: \n\t"
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"movdqa (%0,%2), %%xmm0 \n\t"
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"movdqa 16(%0,%2), %%xmm2 \n\t"
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"movdqu (%1,%2), %%xmm1 \n\t"
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"movdqu 16(%1,%2), %%xmm3 \n\t"
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"psubw %%xmm1, %%xmm0 \n\t"
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"psubw %%xmm3, %%xmm2 \n\t"
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"movdqa %%xmm0, (%0,%2) \n\t"
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"movdqa %%xmm2, 16(%0,%2) \n\t"
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"add $32, %2 \n\t"
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"js 1b \n\t"
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: "+r"(v1), "+r"(v2), "+r"(o)
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);
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}
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static int32_t scalarproduct_int16_sse2(int16_t * v1, int16_t * v2, int order, int shift)
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{
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int res = 0;
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DECLARE_ALIGNED_16(xmm_reg, sh);
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x86_reg o = -(order << 1);
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v1 += order;
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v2 += order;
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sh.a = shift;
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__asm__ volatile(
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"pxor %%xmm7, %%xmm7 \n\t"
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"1: \n\t"
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"movdqu (%0,%3), %%xmm0 \n\t"
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"movdqu 16(%0,%3), %%xmm1 \n\t"
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"pmaddwd (%1,%3), %%xmm0 \n\t"
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"pmaddwd 16(%1,%3), %%xmm1 \n\t"
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"paddd %%xmm0, %%xmm7 \n\t"
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"paddd %%xmm1, %%xmm7 \n\t"
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"add $32, %3 \n\t"
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"js 1b \n\t"
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"movhlps %%xmm7, %%xmm2 \n\t"
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"paddd %%xmm2, %%xmm7 \n\t"
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"psrad %4, %%xmm7 \n\t"
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"pshuflw $0x4E, %%xmm7,%%xmm2 \n\t"
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"paddd %%xmm2, %%xmm7 \n\t"
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"movd %%xmm7, %2 \n\t"
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: "+r"(v1), "+r"(v2), "=r"(res), "+r"(o)
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: "m"(sh)
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);
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return res;
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}
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void dsputil_init_mmx(DSPContext* c, AVCodecContext *avctx)
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{
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mm_flags = mm_support();
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@ -3015,6 +2949,13 @@ void dsputil_init_mmx(DSPContext* c, AVCodecContext *avctx)
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c->float_to_int16_interleave = float_to_int16_interleave_3dn2;
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}
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}
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if(mm_flags & FF_MM_MMX2){
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#if HAVE_YASM
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c->add_int16 = ff_add_int16_mmx2;
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c->sub_int16 = ff_sub_int16_mmx2;
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c->scalarproduct_int16 = ff_scalarproduct_int16_mmx2;
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#endif
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}
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if(mm_flags & FF_MM_SSE){
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c->vorbis_inverse_coupling = vorbis_inverse_coupling_sse;
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c->ac3_downmix = ac3_downmix_sse;
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@ -3033,9 +2974,11 @@ void dsputil_init_mmx(DSPContext* c, AVCodecContext *avctx)
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c->int32_to_float_fmul_scalar = int32_to_float_fmul_scalar_sse2;
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c->float_to_int16 = float_to_int16_sse2;
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c->float_to_int16_interleave = float_to_int16_interleave_sse2;
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c->add_int16 = add_int16_sse2;
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c->sub_int16 = sub_int16_sse2;
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c->scalarproduct_int16 = scalarproduct_int16_sse2;
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#if HAVE_YASM
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c->add_int16 = ff_add_int16_sse2;
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c->sub_int16 = ff_sub_int16_sse2;
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c->scalarproduct_int16 = ff_scalarproduct_int16_sse2;
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#endif
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}
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}
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@ -99,6 +99,81 @@ FLOAT_TO_INT16_INTERLEAVE6 3dn2
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%macro SCALARPRODUCT 1
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; void add_int16(int16_t * v1, int16_t * v2, int order)
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cglobal add_int16_%1, 3,3,2, v1, v2, order
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shl orderq, 1
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add v1q, orderq
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add v2q, orderq
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neg orderq
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.loop:
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movu m0, [v2q + orderq]
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movu m1, [v2q + orderq + mmsize]
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paddw m0, [v1q + orderq]
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paddw m1, [v1q + orderq + mmsize]
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mova [v1q + orderq], m0
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mova [v1q + orderq + mmsize], m1
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add orderq, mmsize*2
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jl .loop
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REP_RET
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; void sub_int16(int16_t * v1, int16_t * v2, int order)
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cglobal sub_int16_%1, 3,3,4, v1, v2, order
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shl orderq, 1
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add v1q, orderq
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add v2q, orderq
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neg orderq
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.loop:
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movu m2, [v2q + orderq]
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movu m3, [v2q + orderq + mmsize]
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mova m0, [v1q + orderq]
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mova m1, [v1q + orderq + mmsize]
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psubw m0, m2
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psubw m1, m3
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mova [v1q + orderq], m0
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mova [v1q + orderq + mmsize], m1
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add orderq, mmsize*2
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jl .loop
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REP_RET
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; int scalarproduct_int16_sse2(int16_t * v1, int16_t * v2, int order, int shift)
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cglobal scalarproduct_int16_%1, 3,3,4, v1, v2, order, shift
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shl orderq, 1
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add v1q, orderq
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add v2q, orderq
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neg orderq
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movd m3, shiftm
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pxor m2, m2
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.loop:
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movu m0, [v1q + orderq]
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movu m1, [v1q + orderq + mmsize]
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pmaddwd m0, [v2q + orderq]
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pmaddwd m1, [v2q + orderq + mmsize]
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paddd m2, m0
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paddd m2, m1
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add orderq, mmsize*2
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jl .loop
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%if mmsize == 16
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movhlps m0, m2
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paddd m2, m0
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psrad m2, m3
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pshuflw m0, m2, 0x4e
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%else
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psrad m2, m3
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pshufw m0, m2, 0x4e
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%endif
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paddd m2, m0
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movd eax, m2
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RET
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%endmacro
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INIT_MMX
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SCALARPRODUCT mmx2
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INIT_XMM
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SCALARPRODUCT sse2
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; void ff_add_hfyu_median_prediction_mmx2(uint8_t *dst, const uint8_t *top, const uint8_t *diff, int w, int *left, int *left_top)
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cglobal add_hfyu_median_prediction_mmx2, 6,6,0, dst, top, diff, w, left, left_top
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movq mm0, [topq]
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