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Merge commit 'a5a0ef5e13a59ff53318a45d77c5624b23229c6f'

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* commit 'a5a0ef5e13a59ff53318a45d77c5624b23229c6f':
  jpegls: return meaningful errors
  sparc: VIS mnemonics

Merged-by: Michael Niedermayer <michaelni@gmx.at>
This commit is contained in:
Michael Niedermayer 2013-05-18 10:04:53 +02:00
commit b53d6a47c5
2 changed files with 13 additions and 34 deletions
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11
libavcodec/jpeglsdec.c
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@ -68,13 +68,13 @@ int ff_jpegls_decode_lse(MJpegDecodeContext *s)
case 2: case 2:
case 3: case 3:
av_log(s->avctx, AV_LOG_ERROR, "palette not supported\n"); av_log(s->avctx, AV_LOG_ERROR, "palette not supported\n");
return -1; return AVERROR(ENOSYS);
case 4: case 4:
av_log(s->avctx, AV_LOG_ERROR, "oversize image not supported\n"); av_log(s->avctx, AV_LOG_ERROR, "oversize image not supported\n");
return -1; return AVERROR(ENOSYS);
default: default:
av_log(s->avctx, AV_LOG_ERROR, "invalid id %d\n", id); av_log(s->avctx, AV_LOG_ERROR, "invalid id %d\n", id);
return -1; return AVERROR_INVALIDDATA;
} }
av_dlog(s->avctx, "ID=%i, T=%i,%i,%i\n", id, s->t1, s->t2, s->t3); av_dlog(s->avctx, "ID=%i, T=%i,%i,%i\n", id, s->t1, s->t2, s->t3);
@ -352,11 +352,10 @@ int ff_jpegls_decode_picture(MJpegDecodeContext *s, int near,
cur += s->picture.linesize[0]; cur += s->picture.linesize[0];
} }
} else if (ilv == 2) { /* sample interleaving */ } else if (ilv == 2) { /* sample interleaving */
av_log(s->avctx, AV_LOG_ERROR, avpriv_report_missing_feature(s->avctx, "Sample interleaved images");
"Sample interleaved images are not supported.\n");
av_free(state); av_free(state);
av_free(zero); av_free(zero);
return -1; return AVERROR_PATCHWELCOME;
} }
if (shift) { /* we need to do point transform or normalize samples */ if (shift) { /* we need to do point transform or normalize samples */

36
libavcodec/sparc/vis.h
View File

@ -150,12 +150,9 @@ static inline int vis_level(void)
#define vis_m2r_2(op,mem1,mem2,rd) \ #define vis_m2r_2(op,mem1,mem2,rd) \
__asm__ volatile (#op "\t[%0 + %1], %%f" #rd : : "r" (mem1), "r" (mem2) ) __asm__ volatile (#op "\t[%0 + %1], %%f" #rd : : "r" (mem1), "r" (mem2) )
static inline void vis_set_gsr(unsigned int _val) static inline void vis_set_gsr(unsigned int val)
{ {
register unsigned int val __asm__("g1"); __asm__ volatile("mov %0,%%asr19"
val = _val;
__asm__ volatile(".word 0xa7804000"
: : "r" (val)); : : "r" (val));
} }
@ -208,36 +205,19 @@ static inline void vis_set_gsr(unsigned int _val)
/* Alignment instructions. */ /* Alignment instructions. */
static inline const void *vis_alignaddr(const void *_ptr) static inline const void *vis_alignaddr(const void *ptr)
{ {
register const void *ptr __asm__("g1"); __asm__ volatile("alignaddr %0, %%g0, %0"
ptr = _ptr;
__asm__ volatile(".word %2"
: "=&r" (ptr) : "=&r" (ptr)
: "0" (ptr), : "0" (ptr));
"i" (vis_opc_base | vis_opf(0x18) |
vis_rs1_s(1) |
vis_rs2_s(0) |
vis_rd_s(1)));
return ptr; return ptr;
} }
static inline void vis_alignaddr_g0(void *_ptr) static inline void vis_alignaddr_g0(void *ptr)
{ {
register void *ptr __asm__("g1"); __asm__ volatile("alignaddr %0, %%g0, %%g0"
: : "r" (ptr));
ptr = _ptr;
__asm__ volatile(".word %2"
: "=&r" (ptr)
: "0" (ptr),
"i" (vis_opc_base | vis_opf(0x18) |
vis_rs1_s(1) |
vis_rs2_s(0) |
vis_rd_s(0)));
} }
#define vis_faligndata(rs1,rs2,rd) vis_dd2d(0x48, rs1, rs2, rd) #define vis_faligndata(rs1,rs2,rd) vis_dd2d(0x48, rs1, rs2, rd)