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lavc/vc1dsp: fix potential overflow in R-V V inv_trans_4
Judging by the coefficients, the last round of add/sub can overflow to 17 bits with a very small probability just as with the 8-point transform. This is not observed under FATE, but better safe than sorry.
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@ -202,13 +202,14 @@ func ff_vc1_inv_trans_4_rvv, zve32x
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vmul.vx v20, v1, t2
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vadd.vv v26, v14, v16 # t3
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vsub.vv v27, v18, v20 # t4
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vadd.vv v0, v24, v26
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vsub.vv v1, v25, v27
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vadd.vv v2, v25, v27
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vsub.vv v3, v24, v26
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.irp n,0,1,2,3
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vssra.vx v\n, v\n, t1 # + 4 >> 3 or + 64 >> 7
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.endr
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vwadd.vv v8, v24, v26
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vwsub.vv v10, v25, v27
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vwadd.vv v12, v25, v27
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vwsub.vv v14, v24, v26
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vnclip.wx v0, v8, t1
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vnclip.wx v1, v10, t1
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vnclip.wx v2, v12, t1
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vnclip.wx v3, v14, t1
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jr t0
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endfunc
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