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https://github.com/FFmpeg/FFmpeg.git
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aarch64/vvc: Add dmvr_hv
dmvr_hv_8_12x20_c: 8.0 ( 1.00x) dmvr_hv_8_12x20_neon: 1.2 ( 6.62x) dmvr_hv_8_20x12_c: 8.0 ( 1.00x) dmvr_hv_8_20x12_neon: 0.9 ( 8.37x) dmvr_hv_8_20x20_c: 12.9 ( 1.00x) dmvr_hv_8_20x20_neon: 1.7 ( 7.62x) dmvr_hv_10_12x20_c: 7.0 ( 1.00x) dmvr_hv_10_12x20_neon: 1.7 ( 4.09x) dmvr_hv_10_20x12_c: 7.0 ( 1.00x) dmvr_hv_10_20x12_neon: 1.7 ( 4.09x) dmvr_hv_10_20x20_c: 11.2 ( 1.00x) dmvr_hv_10_20x20_neon: 2.7 ( 4.15x) dmvr_hv_12_12x20_c: 6.5 ( 1.00x) dmvr_hv_12_12x20_neon: 1.7 ( 3.79x) dmvr_hv_12_20x12_c: 6.5 ( 1.00x) dmvr_hv_12_20x12_neon: 1.7 ( 3.79x) dmvr_hv_12_20x20_c: 10.2 ( 1.00x) dmvr_hv_12_20x20_neon: 2.2 ( 4.64x) Signed-off-by: Zhao Zhili <zhilizhao@tencent.com>
This commit is contained in:
Zhao Zhili
Nuo Mi
parent
0ba9e8d0d4
commit
bcd65ebd8f
@ -85,6 +85,15 @@ W_AVG_FUN(8)
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W_AVG_FUN(10)
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W_AVG_FUN(12)
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#define DMVR_FUN(fn, bd) \
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void ff_vvc_dmvr_ ## fn ## bd ## _neon(int16_t *dst, \
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const uint8_t *_src, ptrdiff_t _src_stride, int height, \
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intptr_t mx, intptr_t my, int width);
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DMVR_FUN(hv_, 8)
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DMVR_FUN(hv_, 10)
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DMVR_FUN(hv_, 12)
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void ff_vvc_dsp_init_aarch64(VVCDSPContext *const c, const int bd)
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{
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int cpu_flags = av_get_cpu_flags();
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@ -157,6 +166,7 @@ void ff_vvc_dsp_init_aarch64(VVCDSPContext *const c, const int bd)
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c->inter.avg = ff_vvc_avg_8_neon;
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c->inter.w_avg = vvc_w_avg_8;
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c->inter.dmvr[1][1] = ff_vvc_dmvr_hv_8_neon;
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for (int i = 0; i < FF_ARRAY_ELEMS(c->sao.band_filter); i++)
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c->sao.band_filter[i] = ff_h26x_sao_band_filter_8x8_8_neon;
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@ -198,12 +208,14 @@ void ff_vvc_dsp_init_aarch64(VVCDSPContext *const c, const int bd)
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} else if (bd == 10) {
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c->inter.avg = ff_vvc_avg_10_neon;
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c->inter.w_avg = vvc_w_avg_10;
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c->inter.dmvr[1][1] = ff_vvc_dmvr_hv_10_neon;
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c->alf.filter[LUMA] = alf_filter_luma_10_neon;
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c->alf.filter[CHROMA] = alf_filter_chroma_10_neon;
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} else if (bd == 12) {
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c->inter.avg = ff_vvc_avg_12_neon;
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c->inter.w_avg = vvc_w_avg_12;
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c->inter.dmvr[1][1] = ff_vvc_dmvr_hv_12_neon;
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c->alf.filter[LUMA] = alf_filter_luma_12_neon;
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c->alf.filter[CHROMA] = alf_filter_chroma_12_neon;
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@ -226,3 +226,310 @@ vvc_avg avg, 12
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vvc_avg w_avg, 8
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vvc_avg w_avg, 10
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vvc_avg w_avg, 12
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/* x0: int16_t *dst
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* x1: const uint8_t *_src
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* x2: ptrdiff_t _src_stride
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* w3: int height
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* x4: intptr_t mx
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* x5: intptr_t my
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* w6: int width
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*/
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function ff_vvc_dmvr_hv_8_neon, export=1
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dst .req x0
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src .req x1
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src_stride .req x2
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height .req w3
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mx .req x4
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my .req x5
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width .req w6
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tmp0 .req x7
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tmp1 .req x8
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sub sp, sp, #(VVC_MAX_PB_SIZE * 4)
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movrel x9, X(ff_vvc_inter_luma_dmvr_filters)
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add x12, x9, mx, lsl #1
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ldrb w10, [x12]
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ldrb w11, [x12, #1]
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mov tmp0, sp
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add tmp1, tmp0, #(VVC_MAX_PB_SIZE * 2)
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// We know the value are positive
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dup v0.8h, w10 // filter_x[0]
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dup v1.8h, w11 // filter_x[1]
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add x12, x9, my, lsl #1
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ldrb w10, [x12]
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ldrb w11, [x12, #1]
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sxtw x6, w6
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movi v30.8h, #(1 << (8 - 7)) // offset1
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movi v31.8h, #8 // offset2
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dup v2.8h, w10 // filter_y[0]
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dup v3.8h, w11 // filter_y[1]
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// Valid value for width can only be 8 + 4, 16 + 4
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cmp width, #16
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mov w10, #0 // start filter_y or not
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add height, height, #1
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sub dst, dst, #(VVC_MAX_PB_SIZE * 2)
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sub src_stride, src_stride, x6
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cset w15, gt // width > 16
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1:
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mov x12, tmp0
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mov x13, tmp1
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mov x14, dst
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cbz w15, 2f
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// width > 16
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ldur q5, [src, #1]
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ldr q4, [src], #16
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uxtl v7.8h, v5.8b
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uxtl2 v17.8h, v5.16b
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uxtl v6.8h, v4.8b
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uxtl2 v16.8h, v4.16b
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mul v6.8h, v6.8h, v0.8h
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mul v16.8h, v16.8h, v0.8h
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mla v6.8h, v7.8h, v1.8h
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mla v16.8h, v17.8h, v1.8h
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add v6.8h, v6.8h, v30.8h
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add v16.8h, v16.8h, v30.8h
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ushr v6.8h, v6.8h, #(8 - 6)
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ushr v7.8h, v16.8h, #(8 - 6)
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stp q6, q7, [x13], #32
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cbz w10, 3f
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ldp q16, q17, [x12], #32
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mul v16.8h, v16.8h, v2.8h
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mul v17.8h, v17.8h, v2.8h
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mla v16.8h, v6.8h, v3.8h
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mla v17.8h, v7.8h, v3.8h
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add v16.8h, v16.8h, v31.8h
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add v17.8h, v17.8h, v31.8h
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ushr v16.8h, v16.8h, #4
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ushr v17.8h, v17.8h, #4
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stp q16, q17, [x14], #32
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b 3f
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2:
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// width > 8
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ldur d5, [src, #1]
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ldr d4, [src], #8
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uxtl v7.8h, v5.8b
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uxtl v6.8h, v4.8b
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mul v6.8h, v6.8h, v0.8h
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mla v6.8h, v7.8h, v1.8h
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add v6.8h, v6.8h, v30.8h
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ushr v6.8h, v6.8h, #(8 - 6)
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str q6, [x13], #16
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cbz w10, 3f
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ldr q16, [x12], #16
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mul v16.8h, v16.8h, v2.8h
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mla v16.8h, v6.8h, v3.8h
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add v16.8h, v16.8h, v31.8h
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ushr v16.8h, v16.8h, #4
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str q16, [x14], #16
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3:
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ldr s5, [src, #1]
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ldr s4, [src], #4
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uxtl v7.8h, v5.8b
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uxtl v6.8h, v4.8b
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mul v6.4h, v6.4h, v0.4h
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mla v6.4h, v7.4h, v1.4h
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add v6.4h, v6.4h, v30.4h
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ushr v6.4h, v6.4h, #(8 - 6)
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str d6, [x13], #8
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cbz w10, 4f
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ldr d16, [x12], #8
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mul v16.4h, v16.4h, v2.4h
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mla v16.4h, v6.4h, v3.4h
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add v16.4h, v16.4h, v31.4h
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ushr v16.4h, v16.4h, #4
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str d16, [x14], #8
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4:
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subs height, height, #1
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mov w10, #1
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add src, src, src_stride
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add dst, dst, #(VVC_MAX_PB_SIZE * 2)
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eor tmp0, tmp0, tmp1
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eor tmp1, tmp0, tmp1
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eor tmp0, tmp0, tmp1
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b.ne 1b
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add sp, sp, #(VVC_MAX_PB_SIZE * 4)
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ret
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endfunc
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function ff_vvc_dmvr_hv_12_neon, export=1
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movi v29.4s, #(12 - 6)
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movi v30.4s, #(1 << (12 - 7)) // offset1
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b 0f
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endfunc
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function ff_vvc_dmvr_hv_10_neon, export=1
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movi v29.4s, #(10 - 6)
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movi v30.4s, #(1 << (10 - 7)) // offset1
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0:
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movi v31.4s, #8 // offset2
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neg v29.4s, v29.4s
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sub sp, sp, #(VVC_MAX_PB_SIZE * 4)
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movrel x9, X(ff_vvc_inter_luma_dmvr_filters)
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add x12, x9, mx, lsl #1
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ldrb w10, [x12]
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ldrb w11, [x12, #1]
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mov tmp0, sp
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add tmp1, tmp0, #(VVC_MAX_PB_SIZE * 2)
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// We know the value are positive
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dup v0.8h, w10 // filter_x[0]
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dup v1.8h, w11 // filter_x[1]
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add x12, x9, my, lsl #1
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ldrb w10, [x12]
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ldrb w11, [x12, #1]
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sxtw x6, w6
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dup v2.8h, w10 // filter_y[0]
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dup v3.8h, w11 // filter_y[1]
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// Valid value for width can only be 8 + 4, 16 + 4
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cmp width, #16
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mov w10, #0 // start filter_y or not
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add height, height, #1
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sub dst, dst, #(VVC_MAX_PB_SIZE * 2)
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sub src_stride, src_stride, x6, lsl #1
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cset w15, gt // width > 16
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1:
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mov x12, tmp0
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mov x13, tmp1
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mov x14, dst
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cbz w15, 2f
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// width > 16
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add x16, src, #2
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ldp q6, q16, [src], #32
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ldp q7, q17, [x16]
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umull v4.4s, v6.4h, v0.4h
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umull2 v5.4s, v6.8h, v0.8h
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umull v18.4s, v16.4h, v0.4h
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umull2 v19.4s, v16.8h, v0.8h
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umlal v4.4s, v7.4h, v1.4h
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umlal2 v5.4s, v7.8h, v1.8h
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umlal v18.4s, v17.4h, v1.4h
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umlal2 v19.4s, v17.8h, v1.8h
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add v4.4s, v4.4s, v30.4s
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add v5.4s, v5.4s, v30.4s
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add v18.4s, v18.4s, v30.4s
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add v19.4s, v19.4s, v30.4s
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ushl v4.4s, v4.4s, v29.4s
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ushl v5.4s, v5.4s, v29.4s
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ushl v18.4s, v18.4s, v29.4s
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ushl v19.4s, v19.4s, v29.4s
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uqxtn v6.4h, v4.4s
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uqxtn2 v6.8h, v5.4s
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uqxtn v7.4h, v18.4s
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uqxtn2 v7.8h, v19.4s
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stp q6, q7, [x13], #32
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cbz w10, 3f
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ldp q4, q5, [x12], #32
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umull v17.4s, v4.4h, v2.4h
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umull2 v18.4s, v4.8h, v2.8h
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umull v19.4s, v5.4h, v2.4h
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umull2 v20.4s, v5.8h, v2.8h
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umlal v17.4s, v6.4h, v3.4h
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umlal2 v18.4s, v6.8h, v3.8h
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umlal v19.4s, v7.4h, v3.4h
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umlal2 v20.4s, v7.8h, v3.8h
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add v17.4s, v17.4s, v31.4s
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add v18.4s, v18.4s, v31.4s
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add v19.4s, v19.4s, v31.4s
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add v20.4s, v20.4s, v31.4s
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ushr v17.4s, v17.4s, #4
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ushr v18.4s, v18.4s, #4
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ushr v19.4s, v19.4s, #4
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ushr v20.4s, v20.4s, #4
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uqxtn v6.4h, v17.4s
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uqxtn2 v6.8h, v18.4s
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uqxtn v7.4h, v19.4s
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uqxtn2 v7.8h, v20.4s
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stp q6, q7, [x14], #32
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b 3f
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2:
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// width > 8
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ldur q7, [src, #2]
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ldr q6, [src], #16
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umull v4.4s, v6.4h, v0.4h
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umull2 v5.4s, v6.8h, v0.8h
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umlal v4.4s, v7.4h, v1.4h
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umlal2 v5.4s, v7.8h, v1.8h
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add v4.4s, v4.4s, v30.4s
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add v5.4s, v5.4s, v30.4s
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ushl v4.4s, v4.4s, v29.4s
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ushl v5.4s, v5.4s, v29.4s
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uqxtn v6.4h, v4.4s
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uqxtn2 v6.8h, v5.4s
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str q6, [x13], #16
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cbz w10, 3f
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ldr q16, [x12], #16
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umull v17.4s, v16.4h, v2.4h
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umull2 v18.4s, v16.8h, v2.8h
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umlal v17.4s, v6.4h, v3.4h
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umlal2 v18.4s, v6.8h, v3.8h
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add v17.4s, v17.4s, v31.4s
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add v18.4s, v18.4s, v31.4s
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ushr v17.4s, v17.4s, #4
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ushr v18.4s, v18.4s, #4
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uqxtn v16.4h, v17.4s
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uqxtn2 v16.8h, v18.4s
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str q16, [x14], #16
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3:
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ldr d7, [src, #2]
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ldr d6, [src], #8
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umull v4.4s, v7.4h, v1.4h
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umlal v4.4s, v6.4h, v0.4h
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add v4.4s, v4.4s, v30.4s
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ushl v4.4s, v4.4s, v29.4s
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uqxtn v6.4h, v4.4s
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str d6, [x13], #8
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cbz w10, 4f
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ldr d16, [x12], #8
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umull v17.4s, v16.4h, v2.4h
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umlal v17.4s, v6.4h, v3.4h
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add v17.4s, v17.4s, v31.4s
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ushr v17.4s, v17.4s, #4
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uqxtn v16.4h, v17.4s
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str d16, [x14], #8
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4:
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subs height, height, #1
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mov w10, #1
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add src, src, src_stride
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add dst, dst, #(VVC_MAX_PB_SIZE * 2)
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eor tmp0, tmp0, tmp1
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eor tmp1, tmp0, tmp1
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eor tmp0, tmp0, tmp1
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b.ne 1b
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add sp, sp, #(VVC_MAX_PB_SIZE * 4)
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ret
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.unreq dst
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.unreq src
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.unreq src_stride
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.unreq height
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.unreq mx
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.unreq my
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.unreq width
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.unreq tmp0
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.unreq tmp1
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endfunc
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