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vp9/x86: intra prediction sse2/32bit support.
Signed-off-by: Michael Niedermayer <michaelni@gmx.at>
This commit is contained in:
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b6e1711223
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bdc1e3e3b2
@ -40,7 +40,7 @@ DECLARE_ALIGNED(8, const uint64_t, ff_pw_53) = 0x0035003500350035ULL;
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DECLARE_ALIGNED(16, const xmm_reg, ff_pw_64) = { 0x0040004000400040ULL, 0x0040004000400040ULL };
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DECLARE_ALIGNED(8, const uint64_t, ff_pw_96) = 0x0060006000600060ULL;
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DECLARE_ALIGNED(8, const uint64_t, ff_pw_128) = 0x0080008000800080ULL;
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DECLARE_ALIGNED(8, const uint64_t, ff_pw_255) = 0x00ff00ff00ff00ffULL;
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DECLARE_ALIGNED(8, const xmm_reg, ff_pw_255) = { 0x00ff00ff00ff00ffULL, 0x00ff00ff00ff00ffULL };
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DECLARE_ALIGNED(32, const ymm_reg, ff_pw_256) = { 0x0100010001000100ULL, 0x0100010001000100ULL,
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0x0100010001000100ULL, 0x0100010001000100ULL };
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DECLARE_ALIGNED(16, const xmm_reg, ff_pw_512) = { 0x0200020002000200ULL, 0x0200020002000200ULL };
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@ -42,7 +42,7 @@ extern const uint64_t ff_pw_53;
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extern const xmm_reg ff_pw_64;
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extern const uint64_t ff_pw_96;
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extern const uint64_t ff_pw_128;
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extern const uint64_t ff_pw_255;
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extern const xmm_reg ff_pw_255;
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extern const xmm_reg ff_pw_512;
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extern const xmm_reg ff_pw_1024;
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extern const xmm_reg ff_pw_2048;
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@ -243,40 +243,58 @@ lpf_funcs(88, 16, avx);
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void ff_vp9_ipred_##type##_##size##x##size##_##opt(uint8_t *dst, ptrdiff_t stride, \
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const uint8_t *l, const uint8_t *a)
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#define ipred_funcs(type, opt) \
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ipred_func(4, type, opt); \
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ipred_func(8, type, opt); \
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ipred_func(16, type, opt); \
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ipred_func(32, type, opt)
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ipred_funcs(dc, ssse3);
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ipred_funcs(dc_left, ssse3);
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ipred_funcs(dc_top, ssse3);
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#undef ipred_funcs
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ipred_func(8, v, mmx);
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ipred_func(16, v, sse2);
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ipred_func(32, v, sse2);
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#define ipred_func_set(size, type, opt1, opt2) \
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ipred_func(size, type, opt1); \
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ipred_func(size, type, opt2)
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#define ipred_dc_funcs(size, opt) \
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ipred_func(size, dc, opt); \
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ipred_func(size, dc_left, opt); \
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ipred_func(size, dc_top, opt)
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#define ipred_funcs(type, opt1, opt2) \
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ipred_func(4, type, opt1); \
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ipred_func_set(8, type, opt1, opt2); \
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ipred_func_set(16, type, opt1, opt2); \
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ipred_func_set(32, type, opt1, opt2)
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ipred_dc_funcs(4, mmxext);
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ipred_dc_funcs(8, mmxext);
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ipred_funcs(h, ssse3, avx);
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ipred_funcs(tm, ssse3, avx);
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ipred_funcs(dl, ssse3, avx);
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ipred_funcs(dr, ssse3, avx);
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ipred_funcs(hu, ssse3, avx);
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ipred_funcs(hd, ssse3, avx);
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ipred_funcs(vl, ssse3, avx);
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ipred_funcs(vr, ssse3, avx);
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#define ipred_dir_tm_funcs(size, opt) \
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ipred_func(size, tm, opt); \
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ipred_func(size, dl, opt); \
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ipred_func(size, dr, opt); \
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ipred_func(size, hd, opt); \
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ipred_func(size, hu, opt); \
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ipred_func(size, vl, opt); \
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ipred_func(size, vr, opt)
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ipred_dir_tm_funcs(4, mmxext);
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ipred_func(16, v, sse);
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ipred_func(32, v, sse);
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ipred_dc_funcs(16, sse2);
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ipred_dc_funcs(32, sse2);
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#define ipred_dir_tm_h_funcs(size, opt) \
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ipred_dir_tm_funcs(size, opt); \
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ipred_func(size, h, opt)
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ipred_dir_tm_h_funcs(8, sse2);
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ipred_dir_tm_h_funcs(16, sse2);
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ipred_dir_tm_h_funcs(32, sse2);
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ipred_func(4, h, sse2);
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#define ipred_all_funcs(size, opt) \
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ipred_dc_funcs(size, opt); \
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ipred_dir_tm_h_funcs(size, opt)
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// FIXME hd/vl_4x4_ssse3 does not exist
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ipred_all_funcs(4, ssse3);
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ipred_all_funcs(8, ssse3);
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ipred_all_funcs(16, ssse3);
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ipred_all_funcs(32, ssse3);
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ipred_dir_tm_h_funcs(8, avx);
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ipred_dir_tm_h_funcs(16, avx);
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ipred_dir_tm_h_funcs(32, avx);
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ipred_func(32, v, avx);
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ipred_func(32, dc, avx2);
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ipred_func(32, dc_left, avx2);
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@ -285,9 +303,14 @@ ipred_func(32, v, avx2);
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ipred_func(32, h, avx2);
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ipred_func(32, tm, avx2);
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#undef ipred_funcs
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#undef ipred_func_set
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ipred_dc_funcs(32, avx2);
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ipred_func(32, h, avx2);
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ipred_func(32, tm, avx2);
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#undef ipred_func
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#undef ipred_dir_tm_h_funcs
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#undef ipred_dir_tm_funcs
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#undef ipred_dc_funcs
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#endif /* HAVE_YASM */
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@ -340,23 +363,32 @@ av_cold void ff_vp9dsp_init_x86(VP9DSPContext *dsp)
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} \
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} while (0)
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#define init_ipred(tx, sz, opt) do { \
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dsp->intra_pred[tx][HOR_PRED] = ff_vp9_ipred_h_##sz##x##sz##_##opt; \
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dsp->intra_pred[tx][DIAG_DOWN_LEFT_PRED] = ff_vp9_ipred_dl_##sz##x##sz##_##opt; \
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dsp->intra_pred[tx][DIAG_DOWN_RIGHT_PRED] = ff_vp9_ipred_dr_##sz##x##sz##_##opt; \
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dsp->intra_pred[tx][HOR_DOWN_PRED] = ff_vp9_ipred_hd_##sz##x##sz##_##opt; \
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dsp->intra_pred[tx][VERT_LEFT_PRED] = ff_vp9_ipred_vl_##sz##x##sz##_##opt; \
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dsp->intra_pred[tx][HOR_UP_PRED] = ff_vp9_ipred_hu_##sz##x##sz##_##opt; \
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if (ARCH_X86_64 || tx != TX_32X32) { \
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dsp->intra_pred[tx][VERT_RIGHT_PRED] = ff_vp9_ipred_vr_##sz##x##sz##_##opt; \
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dsp->intra_pred[tx][TM_VP8_PRED] = ff_vp9_ipred_tm_##sz##x##sz##_##opt; \
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} \
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#define init_ipred(sz, opt, t, e) \
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dsp->intra_pred[TX_##sz##X##sz][e##_PRED] = ff_vp9_ipred_##t##_##sz##x##sz##_##opt
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#define ff_vp9_ipred_hd_4x4_ssse3 ff_vp9_ipred_hd_4x4_mmxext
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#define ff_vp9_ipred_vl_4x4_ssse3 ff_vp9_ipred_vl_4x4_mmxext
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#define init_dir_tm_ipred(sz, opt) do { \
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init_ipred(sz, opt, dl, DIAG_DOWN_LEFT); \
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init_ipred(sz, opt, dr, DIAG_DOWN_RIGHT); \
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init_ipred(sz, opt, hd, HOR_DOWN); \
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init_ipred(sz, opt, vl, VERT_LEFT); \
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init_ipred(sz, opt, hu, HOR_UP); \
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init_ipred(sz, opt, tm, TM_VP8); \
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init_ipred(sz, opt, vr, VERT_RIGHT); \
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} while (0)
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#define init_dc_ipred(tx, sz, opt) do { \
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init_ipred(tx, sz, opt); \
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dsp->intra_pred[tx][DC_PRED] = ff_vp9_ipred_dc_##sz##x##sz##_##opt; \
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dsp->intra_pred[tx][LEFT_DC_PRED] = ff_vp9_ipred_dc_left_##sz##x##sz##_##opt; \
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dsp->intra_pred[tx][TOP_DC_PRED] = ff_vp9_ipred_dc_top_##sz##x##sz##_##opt; \
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#define init_dir_tm_h_ipred(sz, opt) do { \
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init_dir_tm_ipred(sz, opt); \
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init_ipred(sz, opt, h, HOR); \
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} while (0)
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#define init_dc_ipred(sz, opt) do { \
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init_ipred(sz, opt, dc, DC); \
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init_ipred(sz, opt, dc_left, LEFT_DC); \
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init_ipred(sz, opt, dc_top, TOP_DC); \
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} while (0)
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#define init_all_ipred(sz, opt) do { \
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init_dc_ipred(sz, opt); \
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init_dir_tm_h_ipred(sz, opt); \
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} while (0)
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if (EXTERNAL_MMX(cpu_flags)) {
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@ -366,7 +398,7 @@ av_cold void ff_vp9dsp_init_x86(VP9DSPContext *dsp)
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dsp->itxfm_add[4 /* lossless */][ADST_DCT] =
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dsp->itxfm_add[4 /* lossless */][DCT_ADST] =
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dsp->itxfm_add[4 /* lossless */][ADST_ADST] = ff_vp9_iwht_iwht_4x4_add_mmx;
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dsp->intra_pred[TX_8X8][VERT_PRED] = ff_vp9_ipred_v_8x8_mmx;
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init_ipred(8, mmx, v, VERT);
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}
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if (EXTERNAL_MMXEXT(cpu_flags)) {
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@ -375,12 +407,17 @@ av_cold void ff_vp9dsp_init_x86(VP9DSPContext *dsp)
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init_fpel(4, 1, 4, avg, mmxext);
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init_fpel(3, 1, 8, avg, mmxext);
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dsp->itxfm_add[TX_4X4][DCT_DCT] = ff_vp9_idct_idct_4x4_add_mmxext;
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init_dc_ipred(4, mmxext);
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init_dc_ipred(8, mmxext);
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init_dir_tm_ipred(4, mmxext);
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}
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if (EXTERNAL_SSE(cpu_flags)) {
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init_fpel(2, 0, 16, put, sse);
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init_fpel(1, 0, 32, put, sse);
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init_fpel(0, 0, 64, put, sse);
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init_ipred(16, sse, v, VERT);
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init_ipred(32, sse, v, VERT);
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}
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if (EXTERNAL_SSE2(cpu_flags)) {
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@ -405,8 +442,12 @@ av_cold void ff_vp9dsp_init_x86(VP9DSPContext *dsp)
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dsp->itxfm_add[TX_32X32][ADST_DCT] =
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dsp->itxfm_add[TX_32X32][DCT_ADST] =
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dsp->itxfm_add[TX_32X32][DCT_DCT] = ff_vp9_idct_idct_32x32_add_sse2;
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dsp->intra_pred[TX_16X16][VERT_PRED] = ff_vp9_ipred_v_16x16_sse2;
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dsp->intra_pred[TX_32X32][VERT_PRED] = ff_vp9_ipred_v_32x32_sse2;
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init_dc_ipred(16, sse2);
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init_dc_ipred(32, sse2);
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init_dir_tm_h_ipred(8, sse2);
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init_dir_tm_h_ipred(16, sse2);
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init_dir_tm_h_ipred(32, sse2);
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init_ipred(4, sse2, h, HOR);
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}
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if (EXTERNAL_SSSE3(cpu_flags)) {
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@ -429,10 +470,10 @@ av_cold void ff_vp9dsp_init_x86(VP9DSPContext *dsp)
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dsp->itxfm_add[TX_32X32][DCT_ADST] =
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dsp->itxfm_add[TX_32X32][DCT_DCT] = ff_vp9_idct_idct_32x32_add_ssse3;
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init_lpf(ssse3);
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init_dc_ipred(TX_4X4, 4, ssse3);
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init_dc_ipred(TX_8X8, 8, ssse3);
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init_dc_ipred(TX_16X16, 16, ssse3);
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init_dc_ipred(TX_32X32, 32, ssse3);
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init_all_ipred(4, ssse3);
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init_all_ipred(8, ssse3);
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init_all_ipred(16, ssse3);
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init_all_ipred(32, ssse3);
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}
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if (EXTERNAL_AVX(cpu_flags)) {
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@ -451,9 +492,10 @@ av_cold void ff_vp9dsp_init_x86(VP9DSPContext *dsp)
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init_fpel(1, 0, 32, put, avx);
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init_fpel(0, 0, 64, put, avx);
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init_lpf(avx);
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init_ipred(TX_8X8, 8, avx);
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init_ipred(TX_16X16, 16, avx);
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init_ipred(TX_32X32, 32, avx);
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init_dir_tm_h_ipred(8, avx);
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init_dir_tm_h_ipred(16, avx);
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init_dir_tm_h_ipred(32, avx);
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init_ipred(32, avx, v, VERT);
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}
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if (EXTERNAL_AVX2(cpu_flags)) {
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@ -465,12 +507,9 @@ av_cold void ff_vp9dsp_init_x86(VP9DSPContext *dsp)
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init_subpel3_32_64(1, avg, avx2);
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#endif
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}
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dsp->intra_pred[TX_32X32][DC_PRED] = ff_vp9_ipred_dc_32x32_avx2;
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dsp->intra_pred[TX_32X32][LEFT_DC_PRED] = ff_vp9_ipred_dc_left_32x32_avx2;
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dsp->intra_pred[TX_32X32][TOP_DC_PRED] = ff_vp9_ipred_dc_top_32x32_avx2;
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dsp->intra_pred[TX_32X32][VERT_PRED] = ff_vp9_ipred_v_32x32_avx2;
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dsp->intra_pred[TX_32X32][HOR_PRED] = ff_vp9_ipred_h_32x32_avx2;
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dsp->intra_pred[TX_32X32][TM_VP8_PRED] = ff_vp9_ipred_tm_32x32_avx2;
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init_dc_ipred(32, avx2);
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init_ipred(32, avx2, h, HOR);
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init_ipred(32, avx2, tm, TM_VP8);
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}
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#undef init_fpel
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