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GCC-4 fix for AMD-64

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Warning: high cola-affinity here)

Originally committed as revision 15750 to svn://svn.mplayerhq.hu/mplayer/trunk/postproc
This commit is contained in:
Guillaume Poirier 2005-06-18 20:16:19 +00:00
parent 8108551a5c
commit bf0c1b62f8
1 changed files with 4 additions and 4 deletions
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8
postproc/swscale_template.c
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@ -765,14 +765,14 @@ static inline void RENAME(yuv2yuvX)(SwsContext *c, int16_t *lumFilter, int16_t *
asm volatile(
YSCALEYUV2YV12X(0, CHR_MMX_FILTER_OFFSET)
:: "r" (&c->redDither),
"r" (uDest), "m" ((long)chrDstW)
"r" (uDest), "p" ((long)chrDstW)
: "%"REG_a, "%"REG_d, "%"REG_S
);
asm volatile(
YSCALEYUV2YV12X(4096, CHR_MMX_FILTER_OFFSET)
:: "r" (&c->redDither),
"r" (vDest), "m" ((long)chrDstW)
"r" (vDest), "p" ((long)chrDstW)
: "%"REG_a, "%"REG_d, "%"REG_S
);
}
@ -780,7 +780,7 @@ static inline void RENAME(yuv2yuvX)(SwsContext *c, int16_t *lumFilter, int16_t *
asm volatile(
YSCALEYUV2YV12X(0, LUM_MMX_FILTER_OFFSET)
:: "r" (&c->redDither),
"r" (dest), "m" ((long)dstW)
"r" (dest), "p" ((long)dstW)
: "%"REG_a, "%"REG_d, "%"REG_S
);
#else
@ -2547,7 +2547,7 @@ FUNNY_UV_CODE
"cmp %2, %%"REG_a" \n\t"
" jb 1b \n\t"
:: "m" (src1), "m" (dst), "m" ((long)dstWidth), "m" (xInc_shr16), "m" (xInc_mask),
:: "m" (src1), "m" (dst), "p" ((long)dstWidth), "m" (xInc_shr16), "m" (xInc_mask),
"r" (src2)
: "%"REG_a, "%"REG_b, "%ecx", "%"REG_D, "%esi"
);