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Merge commit '25cb0c1a1e66edacc1667acf6818f524c0997f10'
* commit '25cb0c1a1e66edacc1667acf6818f524c0997f10': x86inc: activate REP_RET automatically Merged-by: Michael Niedermayer <michaelni@gmx.at>
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@@ -154,8 +154,7 @@ CPUNOP amdnop
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; Pops anything that was pushed by PROLOGUE, and returns.
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; Pops anything that was pushed by PROLOGUE, and returns.
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; REP_RET:
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; REP_RET:
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; Same, but if it doesn't pop anything it becomes a 2-byte ret, for athlons
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; Use this instead of RET if it's a branch target.
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; which are slow when a normal ret follows a branch.
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; registers:
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; registers:
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; rN and rNq are the native-size register holding function argument N
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; rN and rNq are the native-size register holding function argument N
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@@ -503,7 +502,7 @@ DECLARE_REG 14, R15, 120
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%if mmsize == 32
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%if mmsize == 32
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vzeroupper
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vzeroupper
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%endif
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%endif
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ret
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AUTO_REP_RET
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%endmacro
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%endmacro
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%elif ARCH_X86_64 ; *nix x64 ;=============================================
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%elif ARCH_X86_64 ; *nix x64 ;=============================================
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@@ -550,7 +549,7 @@ DECLARE_REG 14, R15, 72
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%if mmsize == 32
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%if mmsize == 32
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vzeroupper
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vzeroupper
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%endif
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%endif
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ret
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AUTO_REP_RET
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%endmacro
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%endmacro
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%else ; X86_32 ;==============================================================
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%else ; X86_32 ;==============================================================
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@@ -606,7 +605,7 @@ DECLARE_ARG 7, 8, 9, 10, 11, 12, 13, 14
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%if mmsize == 32
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%if mmsize == 32
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vzeroupper
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vzeroupper
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%endif
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%endif
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ret
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AUTO_REP_RET
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%endmacro
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%endmacro
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%endif ;======================================================================
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%endif ;======================================================================
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@@ -620,6 +619,10 @@ DECLARE_ARG 7, 8, 9, 10, 11, 12, 13, 14
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%endmacro
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%endmacro
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%endif
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%endif
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; On AMD cpus <=K10, an ordinary ret is slow if it immediately follows either
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; a branch or a branch target. So switch to a 2-byte form of ret in that case.
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; We can automatically detect "follows a branch", but not a branch target.
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; (SSSE3 is a sufficient condition to know that your cpu doesn't have this problem.)
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%macro REP_RET 0
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%macro REP_RET 0
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%if has_epilogue
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%if has_epilogue
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RET
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RET
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@@ -628,6 +631,29 @@ DECLARE_ARG 7, 8, 9, 10, 11, 12, 13, 14
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%endif
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%endif
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%endmacro
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%endmacro
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%define last_branch_adr $$
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%macro AUTO_REP_RET 0
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%ifndef cpuflags
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times ((last_branch_adr-$)>>31)+1 rep ; times 1 iff $ != last_branch_adr.
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%elif notcpuflag(ssse3)
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times ((last_branch_adr-$)>>31)+1 rep
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%endif
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ret
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%endmacro
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%macro BRANCH_INSTR 0-*
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%rep %0
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%macro %1 1-2 %1
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%2 %1
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%%branch_instr:
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%xdefine last_branch_adr %%branch_instr
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%endmacro
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%rotate 1
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%endrep
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%endmacro
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BRANCH_INSTR jz, je, jnz, jne, jl, jle, jnl, jnle, jg, jge, jng, jnge, ja, jae, jna, jnae, jb, jbe, jnb, jnbe, jc, jnc, js, jns, jo, jno, jp, jnp
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%macro TAIL_CALL 2 ; callee, is_nonadjacent
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%macro TAIL_CALL 2 ; callee, is_nonadjacent
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%if has_epilogue
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%if has_epilogue
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call %1
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call %1
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