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aarch64: vp9itxfm16: Move the load_add_store macro out from the itxfm16 pass2 function
This allows reusing the macro for a separate implementation of the pass2 function. Signed-off-by: Martin Storsjö <martin@martin.st>
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@ -851,6 +851,55 @@ endfunc
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st1 {v4.4s}, [\src], \inc
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st1 {v4.4s}, [\src], \inc
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.endm
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.endm
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.macro load_add_store coef0, coef1, coef2, coef3, coef4, coef5, coef6, coef7
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srshr \coef0, \coef0, #6
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ld1 {v4.4h}, [x0], x1
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srshr \coef1, \coef1, #6
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ld1 {v4.d}[1], [x3], x1
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srshr \coef2, \coef2, #6
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ld1 {v5.4h}, [x0], x1
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srshr \coef3, \coef3, #6
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uaddw \coef0, \coef0, v4.4h
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ld1 {v5.d}[1], [x3], x1
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srshr \coef4, \coef4, #6
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uaddw2 \coef1, \coef1, v4.8h
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ld1 {v6.4h}, [x0], x1
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srshr \coef5, \coef5, #6
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uaddw \coef2, \coef2, v5.4h
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ld1 {v6.d}[1], [x3], x1
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sqxtun v4.4h, \coef0
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srshr \coef6, \coef6, #6
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uaddw2 \coef3, \coef3, v5.8h
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ld1 {v7.4h}, [x0], x1
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sqxtun2 v4.8h, \coef1
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srshr \coef7, \coef7, #6
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uaddw \coef4, \coef4, v6.4h
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ld1 {v7.d}[1], [x3], x1
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umin v4.8h, v4.8h, v8.8h
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sub x0, x0, x1, lsl #2
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sub x3, x3, x1, lsl #2
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sqxtun v5.4h, \coef2
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uaddw2 \coef5, \coef5, v6.8h
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st1 {v4.4h}, [x0], x1
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sqxtun2 v5.8h, \coef3
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uaddw \coef6, \coef6, v7.4h
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st1 {v4.d}[1], [x3], x1
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umin v5.8h, v5.8h, v8.8h
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sqxtun v6.4h, \coef4
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uaddw2 \coef7, \coef7, v7.8h
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st1 {v5.4h}, [x0], x1
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sqxtun2 v6.8h, \coef5
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st1 {v5.d}[1], [x3], x1
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umin v6.8h, v6.8h, v8.8h
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sqxtun v7.4h, \coef6
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st1 {v6.4h}, [x0], x1
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sqxtun2 v7.8h, \coef7
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st1 {v6.d}[1], [x3], x1
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umin v7.8h, v7.8h, v8.8h
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st1 {v7.4h}, [x0], x1
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st1 {v7.d}[1], [x3], x1
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.endm
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// Read a vertical 4x16 slice out of a 16x16 matrix, do a transform on it,
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// Read a vertical 4x16 slice out of a 16x16 matrix, do a transform on it,
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// transpose into a horizontal 16x4 slice and store.
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// transpose into a horizontal 16x4 slice and store.
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// x0 = dst (temp buffer)
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// x0 = dst (temp buffer)
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@ -937,57 +986,8 @@ function \txfm\()16_1d_4x16_pass2_neon
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bl \txfm\()16
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bl \txfm\()16
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dup v8.8h, w13
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dup v8.8h, w13
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.macro load_add_store coef0, coef1, coef2, coef3, coef4, coef5, coef6, coef7
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srshr \coef0, \coef0, #6
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ld1 {v4.4h}, [x0], x1
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srshr \coef1, \coef1, #6
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ld1 {v4.d}[1], [x3], x1
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srshr \coef2, \coef2, #6
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ld1 {v5.4h}, [x0], x1
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srshr \coef3, \coef3, #6
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uaddw \coef0, \coef0, v4.4h
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ld1 {v5.d}[1], [x3], x1
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srshr \coef4, \coef4, #6
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uaddw2 \coef1, \coef1, v4.8h
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ld1 {v6.4h}, [x0], x1
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srshr \coef5, \coef5, #6
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uaddw \coef2, \coef2, v5.4h
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ld1 {v6.d}[1], [x3], x1
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sqxtun v4.4h, \coef0
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srshr \coef6, \coef6, #6
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uaddw2 \coef3, \coef3, v5.8h
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ld1 {v7.4h}, [x0], x1
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sqxtun2 v4.8h, \coef1
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srshr \coef7, \coef7, #6
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uaddw \coef4, \coef4, v6.4h
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ld1 {v7.d}[1], [x3], x1
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umin v4.8h, v4.8h, v8.8h
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sub x0, x0, x1, lsl #2
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sub x3, x3, x1, lsl #2
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sqxtun v5.4h, \coef2
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uaddw2 \coef5, \coef5, v6.8h
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st1 {v4.4h}, [x0], x1
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sqxtun2 v5.8h, \coef3
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uaddw \coef6, \coef6, v7.4h
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st1 {v4.d}[1], [x3], x1
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umin v5.8h, v5.8h, v8.8h
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sqxtun v6.4h, \coef4
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uaddw2 \coef7, \coef7, v7.8h
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st1 {v5.4h}, [x0], x1
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sqxtun2 v6.8h, \coef5
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st1 {v5.d}[1], [x3], x1
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umin v6.8h, v6.8h, v8.8h
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sqxtun v7.4h, \coef6
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st1 {v6.4h}, [x0], x1
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sqxtun2 v7.8h, \coef7
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st1 {v6.d}[1], [x3], x1
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umin v7.8h, v7.8h, v8.8h
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st1 {v7.4h}, [x0], x1
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st1 {v7.d}[1], [x3], x1
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.endm
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load_add_store v16.4s, v17.4s, v18.4s, v19.4s, v20.4s, v21.4s, v22.4s, v23.4s
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load_add_store v16.4s, v17.4s, v18.4s, v19.4s, v20.4s, v21.4s, v22.4s, v23.4s
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load_add_store v24.4s, v25.4s, v26.4s, v27.4s, v28.4s, v29.4s, v30.4s, v31.4s
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load_add_store v24.4s, v25.4s, v26.4s, v27.4s, v28.4s, v29.4s, v30.4s, v31.4s
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.purgem load_add_store
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br x14
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br x14
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endfunc
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endfunc
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