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ARM: NEON optimised vector_fmul
Originally committed as revision 16867 to svn://svn.ffmpeg.org/ffmpeg/trunk
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8915009813
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@ -146,6 +146,8 @@ void ff_h264_idct_add8_neon(uint8_t **dest, const int *block_offset,
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DCTELEM *block, int stride,
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const uint8_t nnzc[6*8]);
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void ff_vector_fmul_neon(float *dst, const float *src, int len);
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void ff_float_to_int16_neon(int16_t *, const float *, long);
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void ff_float_to_int16_interleave_neon(int16_t *, const float **, long, int);
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@ -242,6 +244,8 @@ void ff_dsputil_init_neon(DSPContext *c, AVCodecContext *avctx)
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c->h264_idct_add16intra = ff_h264_idct_add16intra_neon;
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c->h264_idct_add8 = ff_h264_idct_add8_neon;
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c->vector_fmul = ff_vector_fmul_neon;
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if (!(avctx->flags & CODEC_FLAG_BITEXACT)) {
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c->float_to_int16 = ff_float_to_int16_neon;
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c->float_to_int16_interleave = ff_float_to_int16_interleave_neon;
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@ -609,3 +609,43 @@ function ff_float_to_int16_interleave_neon, export=1
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vcvt.s32.f32 q1, q1, #16
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b 6b
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.endfunc
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function ff_vector_fmul_neon, export=1
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mov r3, r0
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subs r2, r2, #8
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vld1.64 {d0-d3}, [r0,:128]!
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vld1.64 {d4-d7}, [r1,:128]!
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vmul.f32 q8, q0, q2
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vmul.f32 q9, q1, q3
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beq 3f
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bics ip, r2, #15
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beq 2f
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1: subs ip, ip, #16
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vld1.64 {d0-d1}, [r0,:128]!
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vld1.64 {d4-d5}, [r1,:128]!
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vmul.f32 q10, q0, q2
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vld1.64 {d2-d3}, [r0,:128]!
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vld1.64 {d6-d7}, [r1,:128]!
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vmul.f32 q11, q1, q3
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vst1.64 {d16-d19},[r3,:128]!
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vld1.64 {d0-d1}, [r0,:128]!
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vld1.64 {d4-d5}, [r1,:128]!
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vmul.f32 q8, q0, q2
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vld1.64 {d2-d3}, [r0,:128]!
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vld1.64 {d6-d7}, [r1,:128]!
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vmul.f32 q9, q1, q3
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vst1.64 {d20-d23},[r3,:128]!
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bne 1b
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ands r2, r2, #15
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beq 3f
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2: vld1.64 {d0-d1}, [r0,:128]!
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vld1.64 {d4-d5}, [r1,:128]!
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vst1.64 {d16-d17},[r3,:128]!
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vmul.f32 q8, q0, q2
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vld1.64 {d2-d3}, [r0,:128]!
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vld1.64 {d6-d7}, [r1,:128]!
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vst1.64 {d18-d19},[r3,:128]!
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vmul.f32 q9, q1, q3
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3: vst1.64 {d16-d19},[r3,:128]!
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bx lr
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.endfunc
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