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Commit Graph

7 Commits

Author SHA1 Message Date
Rémi Denis-Courmont
5afe734b6d lavu/riscv: remove bespoke assembler for MIN
This is no longer necessary as Zbb is now always explicitly required.
2024-05-10 18:59:06 +03:00
Rémi Denis-Courmont
89029baebd lavu/riscv: allow requesting a second extension 2024-05-10 18:59:06 +03:00
Rémi Denis-Courmont
cd6089dc9c riscv: fix builds without Zbb support 2023-11-18 22:01:59 +02:00
Rémi Denis-Courmont
f59a767ccd lavu/riscv: helper macro for VTYPE encoding
On most cases, the vector type (VTYPE) for the RISC-V Vector extension
is supplied as an immediate value, with either of the VSETVLI or
VSETIVLI instructions. There is however a third instruction VSETVL
which takes the vector type from a general purpose register. That is so
the type can be selected at run-time.

This introduces a macro to load a (valid) vector type into a register.
The syntax follows that of VSETVLI and VSETIVLI, with element size,
group multiplier, then tail and mask policies.
2022-10-10 02:22:12 +02:00
Rémi Denis-Courmont
3ba5579e55 riscv: remove unnecessary #include's
Pointed out by Andreas Rheinhardt.
2022-10-05 06:54:56 +02:00
Rémi Denis-Courmont
39357cad37 lavu/riscv: fallback macros for SH{1, 2, 3}ADD
Those mnemonics require the very latest binutils release at the time of
writing. These macros provide seamless backward compatibility.
2022-09-27 13:19:52 +02:00
Rémi Denis-Courmont
746f1ff36a lavu/riscv: initial common header for assembler macros 2022-09-27 13:19:52 +02:00