Rémi Denis-Courmont
e33ce0d9dd
lavu/fixed_dsp: R-V V fmul_window_scaled
...
vector_fmul_window_scaled_fixed_c: 4393.7
vector_fmul_window_scaled_fixed_rvv_i64: 1642.7
2023-11-23 18:57:18 +02:00
Rémi Denis-Courmont
f39a8790e1
lavu/fixed_dsp: R-V V vector_fmul_window
2023-10-09 19:52:28 +03:00
Rémi Denis-Courmont
10eb3b9c9f
lavu/fixed_dsp: R-V V vector_fmul
...
vector_fmul_fixed_c: 4.0
vector_fmul_fixed_rvv_i64: 0.5
2023-10-09 19:52:28 +03:00
Rémi Denis-Courmont
da7a77fb0a
lavu/fixed_dsp: R-V V vector_fmul_reverse
2023-10-09 19:52:28 +03:00
Rémi Denis-Courmont
bf911cc1bf
lavu/fixed_dsp: R-V V vector_fmul_add
...
vector_fmul_add_fixed_c: 2.2
vector_fmul_add_fixed_rvv_i64: 0.5
2023-10-09 19:52:28 +03:00
Rémi Denis-Courmont
eb73d178ea
lavu/fixed_dsp: R-V V scalarproduct
2023-10-07 17:45:39 +03:00
Rémi Denis-Courmont
b6585eb04c
lavu: add/use flag for RISC-V Zba extension
...
The code was blindly assuming that Zbb or V implied Zba. While the
earlier is practically always true, the later broke some QEMU setups,
as V was introduced earlier than Zba.
2023-07-19 19:29:35 +03:00
Rémi Denis-Courmont
c1bb19e263
lavu/fixeddsp: RISC-V V butterflies_fixed
2022-09-27 13:19:52 +02:00