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https://github.com/FFmpeg/FFmpeg.git
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bf8bb94322
* qatar/master: ffmpeg: get rid of the -vglobal option. dct32: Add AVX implementation of 32-point DCT dct32: Change pass 6 permutation to allow for AVX implementation dct32: port SSE 32-point DCT to YASM multiple inclusion guard cleanup avio: document buffer must created with av_malloc() and friends avio: check AVIOContext malloc failure swscale: point out an alternative to sws_getContext svq3: Do initialization after parsing the extradata add changelog entries for 0.7_beta2 mp3lame: add #include required for AV_RB32 macro. Conflicts: Changelog libavcodec/svq3.c libavcodec/x86/dct32_sse.c libavfilter/vsrc_buffer.h Merged-by: Michael Niedermayer <michaelni@gmx.at>
55 lines
2.4 KiB
C
55 lines
2.4 KiB
C
/*
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* Copyright (c) 2000, 2001, 2002 Fabrice Bellard
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*
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* This file is part of FFmpeg.
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*
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* FFmpeg is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* FFmpeg is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with FFmpeg; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef AVUTIL_CPU_H
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#define AVUTIL_CPU_H
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#define AV_CPU_FLAG_FORCE 0x80000000 /* force usage of selected flags (OR) */
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/* lower 16 bits - CPU features */
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#define AV_CPU_FLAG_MMX 0x0001 ///< standard MMX
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#define AV_CPU_FLAG_MMX2 0x0002 ///< SSE integer functions or AMD MMX ext
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#define AV_CPU_FLAG_3DNOW 0x0004 ///< AMD 3DNOW
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#define AV_CPU_FLAG_SSE 0x0008 ///< SSE functions
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#define AV_CPU_FLAG_SSE2 0x0010 ///< PIV SSE2 functions
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#define AV_CPU_FLAG_SSE2SLOW 0x40000000 ///< SSE2 supported, but usually not faster
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#define AV_CPU_FLAG_3DNOWEXT 0x0020 ///< AMD 3DNowExt
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#define AV_CPU_FLAG_SSE3 0x0040 ///< Prescott SSE3 functions
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#define AV_CPU_FLAG_SSE3SLOW 0x20000000 ///< SSE3 supported, but usually not faster
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#define AV_CPU_FLAG_SSSE3 0x0080 ///< Conroe SSSE3 functions
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#define AV_CPU_FLAG_ATOM 0x10000000 ///< Atom processor, some SSSE3 instructions are slower
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#define AV_CPU_FLAG_SSE4 0x0100 ///< Penryn SSE4.1 functions
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#define AV_CPU_FLAG_SSE42 0x0200 ///< Nehalem SSE4.2 functions
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#define AV_CPU_FLAG_AVX 0x4000 ///< AVX functions: requires OS support even if YMM registers aren't used
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#define AV_CPU_FLAG_IWMMXT 0x0100 ///< XScale IWMMXT
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#define AV_CPU_FLAG_ALTIVEC 0x0001 ///< standard
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/**
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* Return the flags which specify extensions supported by the CPU.
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*/
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int av_get_cpu_flags(void);
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/* The following CPU-specific functions shall not be called directly. */
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int ff_get_cpu_flags_arm(void);
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int ff_get_cpu_flags_ppc(void);
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int ff_get_cpu_flags_x86(void);
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#endif /* AVUTIL_CPU_H */
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