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686959e87e
* qatar/master: doxygen: Consistently use '@' instead of '\' for Doxygen markup. Use av_printf_format to check the usage of printf style functions Add av_printf_format, for marking printf style format strings and their parameters ARM: enable thumb for Cortex-M* CPUs nsvdec: Propagate error values instead of returning 0 in nsv_read_header(). build: remove SRC_PATH_BARE variable build: move basic rules and variables to main Makefile build: move special targets to end of main Makefile lavdev: improve feedback in case of invalid frame rate/size vfwcap: prefer "framerate_q" over "fps" in vfw_read_header() v4l2: prefer "framerate_q" over "fps" in v4l2_set_parameters() fbdev: prefer "framerate_q" over "fps" in device context bktr: prefer "framerate" over "fps" for grab_read_header() ALSA: implement channel layout for playback. alsa: support unsigned variants of already supported signed formats. alsa: add support for more formats. ARM: allow building in Thumb2 mode Conflicts: common.mak doc/APIchanges libavcodec/vdpau.h libavdevice/alsa-audio-common.c libavdevice/fbdev.c libavdevice/libdc1394.c libavutil/avutil.h Merged-by: Michael Niedermayer <michaelni@gmx.at>
153 lines
6.4 KiB
ArmAsm
153 lines
6.4 KiB
ArmAsm
/*
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* ARM NEON optimised RDFT
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* Copyright (c) 2009 Mans Rullgard <mans@mansr.com>
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*
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* This file is part of FFmpeg.
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*
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* FFmpeg is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* FFmpeg is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with FFmpeg; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include "asm.S"
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preserve8
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function ff_rdft_calc_neon, export=1
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push {r4-r8,lr}
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ldr r6, [r0, #4] @ inverse
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mov r4, r0
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mov r5, r1
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lsls r6, r6, #31
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bne 1f
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add r0, r4, #20
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bl X(ff_fft_permute_neon)
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add r0, r4, #20
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mov r1, r5
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bl X(ff_fft_calc_neon)
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1:
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ldr r12, [r4, #0] @ nbits
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mov r2, #1
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lsl r12, r2, r12
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add r0, r5, #8
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add r1, r5, r12, lsl #2
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lsr r12, r12, #2
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ldr r2, [r4, #12] @ tcos
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sub r12, r12, #2
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ldr r3, [r4, #16] @ tsin
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mov r7, r0
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sub r1, r1, #8
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mov lr, r1
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mov r8, #-8
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vld1.32 {d0}, [r0,:64]! @ d1[0,1]
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vld1.32 {d1}, [r1,:64], r8 @ d2[0,1]
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vld1.32 {d4}, [r2,:64]! @ tcos[i]
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vld1.32 {d5}, [r3,:64]! @ tsin[i]
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vmov.f32 d18, #0.5 @ k1
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vdup.32 d19, r6
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pld [r0, #32]
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veor d19, d18, d19 @ k2
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vmov.i32 d16, #0
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vmov.i32 d17, #1<<31
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pld [r1, #-32]
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vtrn.32 d16, d17
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pld [r2, #32]
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vrev64.32 d16, d16 @ d16=1,0 d17=0,1
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pld [r3, #32]
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2:
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veor q1, q0, q8 @ -d1[0],d1[1], d2[0],-d2[1]
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vld1.32 {d24}, [r0,:64]! @ d1[0,1]
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vadd.f32 d0, d0, d3 @ d1[0]+d2[0], d1[1]-d2[1]
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vld1.32 {d25}, [r1,:64], r8 @ d2[0,1]
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vadd.f32 d1, d2, d1 @ -d1[0]+d2[0], d1[1]+d2[1]
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veor q3, q12, q8 @ -d1[0],d1[1], d2[0],-d2[1]
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pld [r0, #32]
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vmul.f32 q10, q0, q9 @ ev.re, ev.im, od.im, od.re
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pld [r1, #-32]
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vadd.f32 d0, d24, d7 @ d1[0]+d2[0], d1[1]-d2[1]
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vadd.f32 d1, d6, d25 @ -d1[0]+d2[0], d1[1]+d2[1]
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vmul.f32 q11, q0, q9 @ ev.re, ev.im, od.im, od.re
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veor d7, d21, d16 @ -od.im, od.re
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vrev64.32 d3, d21 @ od.re, od.im
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veor d6, d20, d17 @ ev.re,-ev.im
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veor d2, d3, d16 @ -od.re, od.im
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vmla.f32 d20, d3, d4[1]
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vmla.f32 d20, d7, d5[1]
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vmla.f32 d6, d2, d4[1]
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vmla.f32 d6, d21, d5[1]
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vld1.32 {d4}, [r2,:64]! @ tcos[i]
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veor d7, d23, d16 @ -od.im, od.re
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vld1.32 {d5}, [r3,:64]! @ tsin[i]
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veor d24, d22, d17 @ ev.re,-ev.im
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vrev64.32 d3, d23 @ od.re, od.im
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pld [r2, #32]
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veor d2, d3, d16 @ -od.re, od.im
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pld [r3, #32]
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vmla.f32 d22, d3, d4[0]
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vmla.f32 d22, d7, d5[0]
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vmla.f32 d24, d2, d4[0]
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vmla.f32 d24, d23, d5[0]
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vld1.32 {d0}, [r0,:64]! @ d1[0,1]
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vld1.32 {d1}, [r1,:64], r8 @ d2[0,1]
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vst1.32 {d20}, [r7,:64]!
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vst1.32 {d6}, [lr,:64], r8
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vst1.32 {d22}, [r7,:64]!
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vst1.32 {d24}, [lr,:64], r8
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subs r12, r12, #2
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bgt 2b
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veor q1, q0, q8 @ -d1[0],d1[1], d2[0],-d2[1]
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vadd.f32 d0, d0, d3 @ d1[0]+d2[0], d1[1]-d2[1]
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vadd.f32 d1, d2, d1 @ -d1[0]+d2[0], d1[1]+d2[1]
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ldr r2, [r4, #8] @ sign_convention
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vmul.f32 q10, q0, q9 @ ev.re, ev.im, od.im, od.re
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add r0, r0, #4
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bfc r2, #0, #31
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vld1.32 {d0[0]}, [r0,:32]
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veor d7, d21, d16 @ -od.im, od.re
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vrev64.32 d3, d21 @ od.re, od.im
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veor d6, d20, d17 @ ev.re,-ev.im
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vld1.32 {d22}, [r5,:64]
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vdup.32 d1, r2
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vmov d23, d22
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veor d2, d3, d16 @ -od.re, od.im
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vtrn.32 d22, d23
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veor d0, d0, d1
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veor d23, d23, d17
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vmla.f32 d20, d3, d4[1]
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vmla.f32 d20, d7, d5[1]
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vmla.f32 d6, d2, d4[1]
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vmla.f32 d6, d21, d5[1]
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vadd.f32 d22, d22, d23
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vst1.32 {d20}, [r7,:64]
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vst1.32 {d6}, [lr,:64]
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vst1.32 {d0[0]}, [r0,:32]
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vst1.32 {d22}, [r5,:64]
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cmp r6, #0
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it eq
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popeq {r4-r8,pc}
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vmul.f32 d22, d22, d18
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vst1.32 {d22}, [r5,:64]
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add r0, r4, #20
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mov r1, r5
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bl X(ff_fft_permute_neon)
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add r0, r4, #20
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mov r1, r5
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pop {r4-r8,lr}
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b X(ff_fft_calc_neon)
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endfunc
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