mirror of
https://github.com/FFmpeg/FFmpeg.git
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121 lines
3.9 KiB
NASM
121 lines
3.9 KiB
NASM
;******************************************************************************
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;* VP9 inverse transform x86 SIMD optimizations
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;*
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;* Copyright (C) 2015 Ronald S. Bultje <rsbultje gmail com>
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;*
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;* This file is part of FFmpeg.
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;*
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;* FFmpeg is free software; you can redistribute it and/or
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;* modify it under the terms of the GNU Lesser General Public
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;* License as published by the Free Software Foundation; either
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;* version 2.1 of the License, or (at your option) any later version.
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;*
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;* FFmpeg is distributed in the hope that it will be useful,
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;* but WITHOUT ANY WARRANTY; without even the implied warranty of
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;* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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;* Lesser General Public License for more details.
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;*
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;* You should have received a copy of the GNU Lesser General Public
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;* License along with FFmpeg; if not, write to the Free Software
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;* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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;******************************************************************************
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%include "libavutil/x86/x86util.asm"
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%include "vp9itxfm_template.asm"
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SECTION_RODATA
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cextern pw_1023
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cextern pw_4095
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SECTION .text
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%macro VP9_STORE_2X 6-7 dstq ; reg1, reg2, tmp1, tmp2, min, max, dst
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mova m%3, [%7]
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mova m%4, [%7+strideq]
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paddw m%3, m%1
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paddw m%4, m%2
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pmaxsw m%3, m%5
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pmaxsw m%4, m%5
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pminsw m%3, m%6
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pminsw m%4, m%6
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mova [%7], m%3
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mova [%7+strideq], m%4
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%endmacro
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%macro ZERO_BLOCK 4 ; mem, stride, nnzcpl, zero_reg
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%assign %%y 0
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%rep %3
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%assign %%x 0
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%rep %3*4/mmsize
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mova [%1+%%y+%%x], %4
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%assign %%x (%%x+mmsize)
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%endrep
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%assign %%y (%%y+%2)
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%endrep
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%endmacro
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; the input coefficients are scaled up by 2 bit (which we downscale immediately
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; in the iwht), and is otherwise orthonormally increased by 1 bit per iwht_1d.
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; therefore, a diff of 10-12+sign bit will fit in 12-14+sign bit after scaling,
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; i.e. everything can be done in 15+1bpp words. Since the quant fractional bits
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; add 2 bits, we need to scale before converting to word in 12bpp, since the
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; input will be 16+sign bit which doesn't fit in 15+sign words, but in 10bpp
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; we can scale after converting to words (which is half the instructions),
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; since the input is only 14+sign bit, which fits in 15+sign words directly.
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%macro IWHT4_FN 2 ; bpp, max
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cglobal vp9_iwht_iwht_4x4_add_%1, 3, 3, 8, dst, stride, block, eob
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mova m7, [pw_%2]
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mova m0, [blockq+0*16+0]
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mova m1, [blockq+1*16+0]
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%if %1 >= 12
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mova m4, [blockq+0*16+8]
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mova m5, [blockq+1*16+8]
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psrad m0, 2
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psrad m1, 2
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psrad m4, 2
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psrad m5, 2
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packssdw m0, m4
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packssdw m1, m5
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%else
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packssdw m0, [blockq+0*16+8]
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packssdw m1, [blockq+1*16+8]
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psraw m0, 2
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psraw m1, 2
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%endif
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mova m2, [blockq+2*16+0]
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mova m3, [blockq+3*16+0]
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%if %1 >= 12
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mova m4, [blockq+2*16+8]
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mova m5, [blockq+3*16+8]
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psrad m2, 2
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psrad m3, 2
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psrad m4, 2
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psrad m5, 2
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packssdw m2, m4
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packssdw m3, m5
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%else
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packssdw m2, [blockq+2*16+8]
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packssdw m3, [blockq+3*16+8]
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psraw m2, 2
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psraw m3, 2
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%endif
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VP9_IWHT4_1D
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TRANSPOSE4x4W 0, 1, 2, 3, 4
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VP9_IWHT4_1D
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pxor m6, m6
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VP9_STORE_2X 0, 1, 4, 5, 6, 7
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lea dstq, [dstq+strideq*2]
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VP9_STORE_2X 2, 3, 4, 5, 6, 7
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ZERO_BLOCK blockq, 16, 4, m6
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RET
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%endmacro
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INIT_MMX mmxext
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IWHT4_FN 10, 1023
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INIT_MMX mmxext
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IWHT4_FN 12, 4095
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