mirror of
https://github.com/FFmpeg/FFmpeg.git
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302 lines
12 KiB
ArmAsm
302 lines
12 KiB
ArmAsm
/*
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* ARM NEON optimised MDCT
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* Copyright (c) 2009 Mans Rullgard <mans@mansr.com>
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*
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* This file is part of FFmpeg.
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*
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* FFmpeg is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* FFmpeg is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with FFmpeg; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include "asm.S"
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.text
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#define ff_fft_calc_neon X(ff_fft_calc_neon)
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function ff_imdct_half_neon, export=1
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push {r4-r8,lr}
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mov r12, #1
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ldr lr, [r0, #28] @ mdct_bits
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ldr r4, [r0, #32] @ tcos
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ldr r3, [r0, #8] @ revtab
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lsl r12, r12, lr @ n = 1 << nbits
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lsr lr, r12, #2 @ n4 = n >> 2
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add r7, r2, r12, lsl #1
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mov r12, #-16
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sub r7, r7, #16
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vld2.32 {d16-d17},[r7,:128],r12 @ d16=x,n1 d17=x,n0
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vld2.32 {d0-d1}, [r2,:128]! @ d0 =m0,x d1 =m1,x
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vrev64.32 d17, d17
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vld2.32 {d2,d3}, [r4,:128]! @ d2=c0,c1 d3=s0,s2
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vmul.f32 d6, d17, d2
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vmul.f32 d7, d0, d2
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1:
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subs lr, lr, #2
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ldr r6, [r3], #4
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vmul.f32 d4, d0, d3
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vmul.f32 d5, d17, d3
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vsub.f32 d4, d6, d4
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vadd.f32 d5, d5, d7
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uxth r8, r6, ror #16
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uxth r6, r6
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add r8, r1, r8, lsl #3
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add r6, r1, r6, lsl #3
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beq 1f
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vld2.32 {d16-d17},[r7,:128],r12
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vld2.32 {d0-d1}, [r2,:128]!
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vrev64.32 d17, d17
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vld2.32 {d2,d3}, [r4,:128]! @ d2=c0,c1 d3=s0,s2
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vmul.f32 d6, d17, d2
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vmul.f32 d7, d0, d2
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vst2.32 {d4[0],d5[0]}, [r6,:64]
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vst2.32 {d4[1],d5[1]}, [r8,:64]
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b 1b
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1:
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vst2.32 {d4[0],d5[0]}, [r6,:64]
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vst2.32 {d4[1],d5[1]}, [r8,:64]
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mov r4, r0
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mov r6, r1
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bl ff_fft_calc_neon
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mov r12, #1
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ldr lr, [r4, #28] @ mdct_bits
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ldr r4, [r4, #32] @ tcos
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lsl r12, r12, lr @ n = 1 << nbits
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lsr lr, r12, #3 @ n8 = n >> 3
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add r4, r4, lr, lsl #3
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add r6, r6, lr, lsl #3
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sub r1, r4, #16
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sub r3, r6, #16
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mov r7, #-16
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mov r8, r6
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mov r0, r3
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vld2.32 {d0-d1}, [r3,:128], r7 @ d0 =i1,r1 d1 =i0,r0
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vld2.32 {d20-d21},[r6,:128]! @ d20=i2,r2 d21=i3,r3
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vld2.32 {d16,d18},[r1,:128], r7 @ d16=c1,c0 d18=s1,s0
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1:
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subs lr, lr, #2
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vmul.f32 d7, d0, d18
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vld2.32 {d17,d19},[r4,:128]! @ d17=c2,c3 d19=s2,s3
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vmul.f32 d4, d1, d18
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vmul.f32 d5, d21, d19
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vmul.f32 d6, d20, d19
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vmul.f32 d22, d1, d16
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vmul.f32 d23, d21, d17
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vmul.f32 d24, d0, d16
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vmul.f32 d25, d20, d17
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vadd.f32 d7, d7, d22
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vadd.f32 d6, d6, d23
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vsub.f32 d4, d4, d24
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vsub.f32 d5, d5, d25
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beq 1f
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vld2.32 {d0-d1}, [r3,:128], r7
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vld2.32 {d20-d21},[r6,:128]!
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vld2.32 {d16,d18},[r1,:128], r7 @ d16=c1,c0 d18=s1,s0
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vrev64.32 q3, q3
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vst2.32 {d4,d6}, [r0,:128], r7
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vst2.32 {d5,d7}, [r8,:128]!
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b 1b
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1:
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vrev64.32 q3, q3
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vst2.32 {d4,d6}, [r0,:128]
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vst2.32 {d5,d7}, [r8,:128]
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pop {r4-r8,pc}
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.endfunc
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function ff_imdct_calc_neon, export=1
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push {r4-r6,lr}
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ldr r3, [r0, #28]
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mov r4, #1
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mov r5, r1
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lsl r4, r4, r3
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add r1, r1, r4
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bl ff_imdct_half_neon
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add r0, r5, r4, lsl #2
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add r1, r5, r4, lsl #1
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sub r0, r0, #8
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sub r2, r1, #16
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mov r3, #-16
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mov r6, #-8
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vmov.i32 d30, #1<<31
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1:
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vld1.32 {d0-d1}, [r2,:128], r3
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pld [r0, #-16]
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vrev64.32 q0, q0
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vld1.32 {d2-d3}, [r1,:128]!
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veor d4, d1, d30
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pld [r2, #-16]
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vrev64.32 q1, q1
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veor d5, d0, d30
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vst1.32 {d2}, [r0,:64], r6
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vst1.32 {d3}, [r0,:64], r6
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vst1.32 {d4-d5}, [r5,:128]!
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subs r4, r4, #16
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bgt 1b
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pop {r4-r6,pc}
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.endfunc
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function ff_mdct_calc_neon, export=1
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push {r4-r10,lr}
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mov r12, #1
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ldr lr, [r0, #28] @ mdct_bits
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ldr r4, [r0, #32] @ tcos
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ldr r3, [r0, #8] @ revtab
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lsl lr, r12, lr @ n = 1 << nbits
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add r7, r2, lr @ in4u
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sub r9, r7, #16 @ in4d
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add r2, r7, lr, lsl #1 @ in3u
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add r8, r9, lr, lsl #1 @ in3d
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add r5, r4, lr, lsl #1
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sub r5, r5, #16
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sub r3, r3, #4
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mov r12, #-16
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vld2.32 {d16,d18},[r9,:128],r12 @ in0u0,in0u1 in4d1,in4d0
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vld2.32 {d17,d19},[r8,:128],r12 @ in2u0,in2u1 in3d1,in3d0
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vld2.32 {d0, d2}, [r7,:128]! @ in4u0,in4u1 in2d1,in2d0
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vrev64.32 q9, q9 @ in4d0,in4d1 in3d0,in3d1
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vld2.32 {d1, d3}, [r2,:128]! @ in3u0,in3u1 in1d1,in1d0
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vsub.f32 d0, d18, d0 @ in4d-in4u I
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vld2.32 {d20,d21},[r4,:128]! @ c0,c1 s0,s1
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vrev64.32 q1, q1 @ in2d0,in2d1 in1d0,in1d1
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vld2.32 {d30,d31},[r5,:128],r12 @ c2,c3 s2,s3
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vadd.f32 d1, d1, d19 @ in3u+in3d -R
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vsub.f32 d16, d16, d2 @ in0u-in2d R
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vadd.f32 d17, d17, d3 @ in2u+in1d -I
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1:
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vmul.f32 d7, d0, d21 @ I*s
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ldr r10, [r3, lr, lsr #1]
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vmul.f32 d6, d1, d20 @ -R*c
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ldr r6, [r3, #4]!
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vmul.f32 d4, d1, d21 @ -R*s
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vmul.f32 d5, d0, d20 @ I*c
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vmul.f32 d24, d16, d30 @ R*c
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vmul.f32 d25, d17, d31 @ -I*s
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vmul.f32 d22, d16, d31 @ R*s
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vmul.f32 d23, d17, d30 @ I*c
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subs lr, lr, #16
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vsub.f32 d6, d6, d7 @ -R*c-I*s
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vadd.f32 d7, d4, d5 @ -R*s+I*c
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vsub.f32 d24, d25, d24 @ I*s-R*c
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vadd.f32 d25, d22, d23 @ R*s-I*c
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beq 1f
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mov r12, #-16
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vld2.32 {d16,d18},[r9,:128],r12 @ in0u0,in0u1 in4d1,in4d0
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vld2.32 {d17,d19},[r8,:128],r12 @ in2u0,in2u1 in3d1,in3d0
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vneg.f32 d7, d7 @ R*s-I*c
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vld2.32 {d0, d2}, [r7,:128]! @ in4u0,in4u1 in2d1,in2d0
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vrev64.32 q9, q9 @ in4d0,in4d1 in3d0,in3d1
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vld2.32 {d1, d3}, [r2,:128]! @ in3u0,in3u1 in1d1,in1d0
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vsub.f32 d0, d18, d0 @ in4d-in4u I
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vld2.32 {d20,d21},[r4,:128]! @ c0,c1 s0,s1
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vrev64.32 q1, q1 @ in2d0,in2d1 in1d0,in1d1
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vld2.32 {d30,d31},[r5,:128],r12 @ c2,c3 s2,s3
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vadd.f32 d1, d1, d19 @ in3u+in3d -R
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vsub.f32 d16, d16, d2 @ in0u-in2d R
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vadd.f32 d17, d17, d3 @ in2u+in1d -I
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uxth r12, r6, ror #16
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uxth r6, r6
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add r12, r1, r12, lsl #3
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add r6, r1, r6, lsl #3
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vst2.32 {d6[0],d7[0]}, [r6,:64]
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vst2.32 {d6[1],d7[1]}, [r12,:64]
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uxth r6, r10, ror #16
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uxth r10, r10
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add r6 , r1, r6, lsl #3
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add r10, r1, r10, lsl #3
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vst2.32 {d24[0],d25[0]},[r10,:64]
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vst2.32 {d24[1],d25[1]},[r6,:64]
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b 1b
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1:
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vneg.f32 d7, d7 @ R*s-I*c
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uxth r12, r6, ror #16
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uxth r6, r6
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add r12, r1, r12, lsl #3
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add r6, r1, r6, lsl #3
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vst2.32 {d6[0],d7[0]}, [r6,:64]
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vst2.32 {d6[1],d7[1]}, [r12,:64]
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uxth r6, r10, ror #16
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uxth r10, r10
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add r6 , r1, r6, lsl #3
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add r10, r1, r10, lsl #3
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vst2.32 {d24[0],d25[0]},[r10,:64]
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vst2.32 {d24[1],d25[1]},[r6,:64]
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mov r4, r0
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mov r6, r1
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bl ff_fft_calc_neon
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mov r12, #1
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ldr lr, [r4, #28] @ mdct_bits
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ldr r4, [r4, #32] @ tcos
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lsl r12, r12, lr @ n = 1 << nbits
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lsr lr, r12, #3 @ n8 = n >> 3
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add r4, r4, lr, lsl #3
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add r6, r6, lr, lsl #3
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sub r1, r4, #16
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sub r3, r6, #16
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mov r7, #-16
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mov r8, r6
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mov r0, r3
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vld2.32 {d0-d1}, [r3,:128], r7 @ d0 =r1,i1 d1 =r0,i0
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vld2.32 {d20-d21},[r6,:128]! @ d20=r2,i2 d21=r3,i3
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vld2.32 {d16,d18},[r1,:128], r7 @ c1,c0 s1,s0
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1:
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subs lr, lr, #2
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vmul.f32 d7, d0, d18 @ r1*s1,r0*s0
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vld2.32 {d17,d19},[r4,:128]! @ c2,c3 s2,s3
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vmul.f32 d4, d1, d18 @ i1*s1,i0*s0
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vmul.f32 d5, d21, d19 @ i2*s2,i3*s3
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vmul.f32 d6, d20, d19 @ r2*s2,r3*s3
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vmul.f32 d24, d0, d16 @ r1*c1,r0*c0
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vmul.f32 d25, d20, d17 @ r2*c2,r3*c3
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vmul.f32 d22, d21, d17 @ i2*c2,i3*c3
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vmul.f32 d23, d1, d16 @ i1*c1,i0*c0
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vadd.f32 d4, d4, d24 @ i1*s1+r1*c1,i0*s0+r0*c0
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vadd.f32 d5, d5, d25 @ i2*s2+r2*c2,i3*s3+r3*c3
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vsub.f32 d6, d22, d6 @ i2*c2-r2*s2,i3*c3-r3*s3
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vsub.f32 d7, d23, d7 @ i1*c1-r1*s1,i0*c0-r0*s0
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vneg.f32 q2, q2
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beq 1f
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vld2.32 {d0-d1}, [r3,:128], r7
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vld2.32 {d20-d21},[r6,:128]!
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vld2.32 {d16,d18},[r1,:128], r7 @ c1,c0 s1,s0
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vrev64.32 q3, q3
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vst2.32 {d4,d6}, [r0,:128], r7
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vst2.32 {d5,d7}, [r8,:128]!
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b 1b
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1:
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vrev64.32 q3, q3
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vst2.32 {d4,d6}, [r0,:128]
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vst2.32 {d5,d7}, [r8,:128]
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pop {r4-r10,pc}
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.endfunc
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