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3221aba879
x64 always has MMX, MMXEXT, SSE and SSE2 and this means that some functions for MMX, MMXEXT and 3dnow are always overridden by other functions (unless one e.g. explicitly disables SSE2) for x64. So given that the only systems that benefit from these functions are truely ancient 32bit x86s they are removed. Signed-off-by: Andreas Rheinhardt <andreas.rheinhardt@outlook.com>
150 lines
5.4 KiB
NASM
150 lines
5.4 KiB
NASM
; Chinese AVS video (AVS1-P2, JiZhun profile) decoder
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; Copyright (c) 2006 Stefan Gehrer <stefan.gehrer@gmx.de>
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;
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; MMX-optimized DSP functions, based on H.264 optimizations by
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; Michael Niedermayer and Loren Merritt
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; Conversion from gcc syntax to x264asm syntax with modifications
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; by Ronald S. Bultje <rsbultje@gmail.com>
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;
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; This file is part of FFmpeg.
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;
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; FFmpeg is free software; you can redistribute it and/or
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; modify it under the terms of the GNU Lesser General Public
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; License as published by the Free Software Foundation; either
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; version 2.1 of the License, or (at your option) any later version.
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;
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; FFmpeg is distributed in the hope that it will be useful,
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; but WITHOUT ANY WARRANTY; without even the implied warranty of
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; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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; Lesser General Public License for more details.
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;
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; You should have received a copy of the GNU Lesser General Public License
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; along with FFmpeg; if not, write to the Free Software Foundation,
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; Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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%include "libavutil/x86/x86util.asm"
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cextern pw_4
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cextern pw_64
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SECTION .text
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%macro CAVS_IDCT8_1D 2-3 1 ; source, round, init_load
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%if %3 == 1
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mova m4, [%1+7*16] ; m4 = src7
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mova m5, [%1+1*16] ; m5 = src1
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mova m2, [%1+5*16] ; m2 = src5
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mova m7, [%1+3*16] ; m7 = src3
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%else
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SWAP 1, 7
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SWAP 4, 6
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%endif
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mova m0, m4
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mova m3, m5
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mova m6, m2
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mova m1, m7
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paddw m4, m4 ; m4 = 2*src7
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paddw m3, m3 ; m3 = 2*src1
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paddw m6, m6 ; m6 = 2*src5
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paddw m1, m1 ; m1 = 2*src3
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paddw m0, m4 ; m0 = 3*src7
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paddw m5, m3 ; m5 = 3*src1
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paddw m2, m6 ; m2 = 3*src5
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paddw m7, m1 ; m7 = 3*src3
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psubw m5, m4 ; m5 = 3*src1 - 2*src7 = a0
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paddw m7, m6 ; m7 = 3*src3 - 2*src5 = a1
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psubw m1, m2 ; m1 = 2*src3 - 3*src5 = a2
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paddw m3, m0 ; m3 = 2*src1 - 3*src7 = a3
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mova m4, m5
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mova m6, m7
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mova m0, m3
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mova m2, m1
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SUMSUB_BA w, 7, 5 ; m7 = a0 + a1, m5 = a0 - a1
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paddw m7, m3 ; m7 = a0 + a1 + a3
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paddw m5, m1 ; m5 = a0 - a1 + a2
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paddw m7, m7
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paddw m5, m5
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paddw m7, m6 ; m7 = b4
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paddw m5, m4 ; m5 = b5
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SUMSUB_BA w, 1, 3 ; m1 = a3 + a2, m3 = a3 - a2
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psubw m4, m1 ; m4 = a0 - a2 - a3
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mova m1, m4 ; m1 = a0 - a2 - a3
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psubw m3, m6 ; m3 = a3 - a2 - a1
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paddw m1, m1
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paddw m3, m3
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psubw m1, m2 ; m1 = b7
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paddw m3, m0 ; m3 = b6
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mova m2, [%1+2*16] ; m2 = src2
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mova m6, [%1+6*16] ; m6 = src6
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mova m4, m2
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mova m0, m6
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psllw m4, 2 ; m4 = 4*src2
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psllw m6, 2 ; m6 = 4*src6
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paddw m2, m4 ; m2 = 5*src2
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paddw m0, m6 ; m0 = 5*src6
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paddw m2, m2
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paddw m0, m0
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psubw m4, m0 ; m4 = 4*src2 - 10*src6 = a7
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paddw m6, m2 ; m6 = 4*src6 + 10*src2 = a6
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mova m2, [%1+0*16] ; m2 = src0
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mova m0, [%1+4*16] ; m0 = src4
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SUMSUB_BA w, 0, 2 ; m0 = src0 + src4, m2 = src0 - src4
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psllw m0, 3
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psllw m2, 3
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paddw m0, %2 ; add rounding bias
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paddw m2, %2 ; add rounding bias
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SUMSUB_BA w, 6, 0 ; m6 = a4 + a6, m0 = a4 - a6
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SUMSUB_BA w, 4, 2 ; m4 = a5 + a7, m2 = a5 - a7
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SUMSUB_BA w, 7, 6 ; m7 = dst0, m6 = dst7
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SUMSUB_BA w, 5, 4 ; m5 = dst1, m4 = dst6
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SUMSUB_BA w, 3, 2 ; m3 = dst2, m2 = dst5
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SUMSUB_BA w, 1, 0 ; m1 = dst3, m0 = dst4
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%endmacro
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INIT_XMM sse2
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cglobal cavs_idct8, 2, 2, 8 + ARCH_X86_64, 0 - 8 * 16, out, in
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CAVS_IDCT8_1D inq, [pw_4]
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psraw m7, 3
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psraw m6, 3
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psraw m5, 3
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psraw m4, 3
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psraw m3, 3
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psraw m2, 3
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psraw m1, 3
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psraw m0, 3
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%if ARCH_X86_64
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TRANSPOSE8x8W 7, 5, 3, 1, 0, 2, 4, 6, 8
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mova [rsp+4*16], m0
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%else
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mova [rsp+0*16], m4
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TRANSPOSE8x8W 7, 5, 3, 1, 0, 2, 4, 6, [rsp+0*16], [rsp+4*16], 1
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%endif
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mova [rsp+0*16], m7
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mova [rsp+2*16], m3
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mova [rsp+6*16], m4
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CAVS_IDCT8_1D rsp, [pw_64], 0
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psraw m7, 7
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psraw m6, 7
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psraw m5, 7
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psraw m4, 7
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psraw m3, 7
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psraw m2, 7
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psraw m1, 7
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psraw m0, 7
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mova [outq+0*16], m7
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mova [outq+1*16], m5
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mova [outq+2*16], m3
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mova [outq+3*16], m1
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mova [outq+4*16], m0
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mova [outq+5*16], m2
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mova [outq+6*16], m4
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mova [outq+7*16], m6
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RET
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