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da1ba4e88b
movd needs explicit register size prefix for NASM. Signed-off-by: Reimar Döffinger <Reimar.Doeffinger@gmx.de>
208 lines
4.6 KiB
NASM
208 lines
4.6 KiB
NASM
;******************************************************************************
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;* MMX/SSE2-optimized functions for the RV40 decoder
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;* Copyright (C) 2012 Christophe Gisquet <christophe.gisquet@gmail.com>
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;*
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;* This file is part of Libav.
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;*
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;* Libav is free software; you can redistribute it and/or
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;* modify it under the terms of the GNU Lesser General Public
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;* License as published by the Free Software Foundation; either
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;* version 2.1 of the License, or (at your option) any later version.
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;*
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;* Libav is distributed in the hope that it will be useful,
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;* but WITHOUT ANY WARRANTY; without even the implied warranty of
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;* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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;* Lesser General Public License for more details.
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;*
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;* You should have received a copy of the GNU Lesser General Public
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;* License along with Libav; if not, write to the Free Software
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;* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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;******************************************************************************
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%include "x86inc.asm"
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%include "x86util.asm"
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SECTION_RODATA
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align 16
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shift_round: times 8 dw 1 << (16 - 6)
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cextern pw_16
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SECTION .text
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; %1=5bits weights?, %2=dst %3=src1 %4=src3 %5=stride if sse2
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%macro RV40_WCORE 4-5
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movh m4, [%3 + 0]
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movh m5, [%4 + 0]
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%if %0 == 4
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%define OFFSET mmsize / 2
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%else
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; 8x8 block and sse2, stride was provided
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%define OFFSET %5
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%endif
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movh m6, [%3 + OFFSET]
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movh m7, [%4 + OFFSET]
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%if %1 == 0
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; 14bits weights
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punpcklbw m4, m0
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punpcklbw m5, m0
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punpcklbw m6, m0
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punpcklbw m7, m0
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psllw m4, 7
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psllw m5, 7
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psllw m6, 7
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psllw m7, 7
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pmulhw m4, m3
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pmulhw m5, m2
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pmulhw m6, m3
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pmulhw m7, m2
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paddw m4, m5
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paddw m6, m7
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%else
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; 5bits weights
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%if cpuflag(ssse3)
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punpcklbw m4, m5
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punpcklbw m6, m7
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pmaddubsw m4, m3
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pmaddubsw m6, m3
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%else
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punpcklbw m4, m0
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punpcklbw m5, m0
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punpcklbw m6, m0
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punpcklbw m7, m0
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pmullw m4, m3
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pmullw m5, m2
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pmullw m6, m3
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pmullw m7, m2
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paddw m4, m5
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paddw m6, m7
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%endif
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%endif
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; bias and shift down
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%if cpuflag(ssse3)
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pmulhrsw m4, m1
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pmulhrsw m6, m1
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%else
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paddw m4, m1
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paddw m6, m1
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psrlw m4, 5
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psrlw m6, 5
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%endif
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packuswb m4, m6
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%if %0 == 5
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; Only called for 8x8 blocks and sse2
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movh [%2 + 0], m4
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movhps [%2 + %5], m4
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%else
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mova [%2], m4
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%endif
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%endmacro
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%macro MAIN_LOOP 2
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%if mmsize == 8
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RV40_WCORE %2, r0, r1, r2
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%if %1 == 16
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RV40_WCORE %2, r0 + 8, r1 + 8, r2 + 8
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%endif
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; Prepare for next loop
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add r0, r5
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add r1, r5
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add r2, r5
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%else
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%ifidn %1, 8
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RV40_WCORE %2, r0, r1, r2, r5
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; Prepare 2 next lines
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lea r0, [r0 + 2 * r5]
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lea r1, [r1 + 2 * r5]
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lea r2, [r2 + 2 * r5]
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%else
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RV40_WCORE %2, r0, r1, r2
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; Prepare single next line
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add r0, r5
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add r1, r5
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add r2, r5
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%endif
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%endif
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dec r6
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%endmacro
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; rv40_weight_func_%1(uint8_t *dst, uint8_t *src1, uint8_t *src2, int w1, int w2, int stride)
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; %1=size %2=num of xmm regs
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%macro RV40_WEIGHT 2
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cglobal rv40_weight_func_%1, 6, 7, %2
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%if cpuflag(ssse3)
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mova m1, [shift_round]
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%else
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mova m1, [pw_16]
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%endif
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pxor m0, m0
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mov r6, r3
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or r6, r4
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; The weights are FP0.14 notation of fractions depending on pts.
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; For timebases without rounding error (i.e. PAL), the fractions
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; can be simplified, and several operations can be avoided.
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; Therefore, we check here whether they are multiples of 2^9 for
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; those simplifications to occur.
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and r6, 0x1FF
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; Set loop counter and increments
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%if mmsize == 8
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mov r6, %1
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%else
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mov r6, (%1 * %1) / mmsize
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%endif
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; Use result of test now
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jz .loop_512
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movd m2, r3d
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movd m3, r4d
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SPLATW m2, m2
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SPLATW m3, m3
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.loop:
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MAIN_LOOP %1, 0
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jnz .loop
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REP_RET
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; Weights are multiple of 512, which allows some shortcuts
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.loop_512:
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sar r3, 9
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sar r4, 9
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movd m2, r3d
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movd m3, r4d
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%if cpuflag(ssse3)
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punpcklbw m3, m2
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SPLATW m3, m3
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%else
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SPLATW m2, m2
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SPLATW m3, m3
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%endif
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.loop2:
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MAIN_LOOP %1, 1
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jnz .loop2
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REP_RET
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%endmacro
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INIT_MMX mmx
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RV40_WEIGHT 8, 0
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RV40_WEIGHT 16, 0
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INIT_XMM sse2
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RV40_WEIGHT 8, 8
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RV40_WEIGHT 16, 8
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INIT_XMM ssse3
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RV40_WEIGHT 8, 8
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RV40_WEIGHT 16, 8
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