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a0fc780a20
3% faster dts decoding on a cortex-a57.
cortex-a57 cortex-a53
int32_to_float_fmul_array8_c: 1270.9 4475.6
int32_to_float_fmul_array8_neon: 328.6 569.2
int32_to_float_fmul_scalar_c: 928.5 4119.6
int32_to_float_fmul_scalar_neon: 309.1 524.1
77 lines
2.7 KiB
ArmAsm
77 lines
2.7 KiB
ArmAsm
/*
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* ARM NEON optimised Format Conversion Utils
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* Copyright (c) 2008 Mans Rullgard <mans@mansr.com>
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* Copyright (c) 2015 Janne Grunau <janne-libav@jannau.net>
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*
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* This file is part of Libav.
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*
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* Libav is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* Libav is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with Libav; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include "config.h"
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#include "libavutil/aarch64/asm.S"
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function ff_int32_to_float_fmul_scalar_neon, export=1
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ld1 {v1.4s,v2.4s}, [x1], #32
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scvtf v1.4s, v1.4s
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scvtf v2.4s, v2.4s
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1:
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subs w2, w2, #8
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fmul v3.4s, v1.4s, v0.s[0]
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fmul v4.4s, v2.4s, v0.s[0]
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b.le 2f
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ld1 {v1.4s,v2.4s}, [x1], #32
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st1 {v3.4s,v4.4s}, [x0], #32
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scvtf v1.4s, v1.4s
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scvtf v2.4s, v2.4s
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b 1b
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2:
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st1 {v3.4s,v4.4s}, [x0]
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ret
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endfunc
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function ff_int32_to_float_fmul_array8_neon, export=1
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lsr w4, w4, #3
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subs w5, w4, #1
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b.eq 1f
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2:
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ld1 {v0.4s,v1.4s}, [x2], #32
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ld1 {v2.4s,v3.4s}, [x2], #32
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scvtf v0.4s, v0.4s
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scvtf v1.4s, v1.4s
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ld1 {v16.2s}, [x3], #8
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scvtf v2.4s, v2.4s
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scvtf v3.4s, v3.4s
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fmul v4.4s, v0.4s, v16.s[0]
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fmul v5.4s, v1.4s, v16.s[0]
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fmul v6.4s, v2.4s, v16.s[1]
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fmul v7.4s, v3.4s, v16.s[1]
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st1 {v4.4s,v5.4s}, [x1], #32
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st1 {v6.4s,v7.4s}, [x1], #32
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subs w5, w5, #2
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b.gt 2b
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b.eq 1f
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ret
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1:
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ld1 {v0.4s,v1.4s}, [x2]
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ld1 {v16.s}[0], [x3]
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scvtf v0.4s, v0.4s
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scvtf v1.4s, v1.4s
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fmul v4.4s, v0.4s, v16.s[0]
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fmul v5.4s, v1.4s, v16.s[0]
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st1 {v4.4s,v5.4s}, [x1]
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ret
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endfunc
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