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https://github.com/FFmpeg/FFmpeg.git
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3a2d1465c8
* commit '2d60444331fca1910510038dd3817bea885c2367': dsputil: Split motion estimation compare bits off into their own context Conflicts: configure libavcodec/Makefile libavcodec/arm/Makefile libavcodec/dvenc.c libavcodec/error_resilience.c libavcodec/h264.h libavcodec/h264_slice.c libavcodec/me_cmp.c libavcodec/me_cmp.h libavcodec/motion_est.c libavcodec/motion_est_template.c libavcodec/mpeg4videoenc.c libavcodec/mpegvideo.c libavcodec/mpegvideo_enc.c libavcodec/x86/Makefile libavcodec/x86/me_cmp_init.c Merged-by: Michael Niedermayer <michaelni@gmx.at>
245 lines
8.3 KiB
ArmAsm
245 lines
8.3 KiB
ArmAsm
/*
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* Copyright (c) 2009 Mans Rullgard <mans@mansr.com>
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*
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* This file is part of FFmpeg.
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*
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* FFmpeg is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* FFmpeg is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with FFmpeg; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include "libavutil/arm/asm.S"
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function ff_pix_abs16_armv6, export=1
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ldr r0, [sp]
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push {r4-r9, lr}
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mov r12, #0
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mov lr, #0
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ldm r1, {r4-r7}
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ldr r8, [r2]
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1:
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ldr r9, [r2, #4]
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pld [r1, r3]
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usada8 r12, r4, r8, r12
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ldr r8, [r2, #8]
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pld [r2, r3]
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usada8 lr, r5, r9, lr
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ldr r9, [r2, #12]
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usada8 r12, r6, r8, r12
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subs r0, r0, #1
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usada8 lr, r7, r9, lr
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beq 2f
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add r1, r1, r3
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ldm r1, {r4-r7}
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add r2, r2, r3
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ldr r8, [r2]
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b 1b
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2:
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add r0, r12, lr
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pop {r4-r9, pc}
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endfunc
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function ff_pix_abs16_x2_armv6, export=1
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ldr r12, [sp]
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push {r4-r11, lr}
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mov r0, #0
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mov lr, #1
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orr lr, lr, lr, lsl #8
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orr lr, lr, lr, lsl #16
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1:
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ldr r8, [r2]
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ldr r9, [r2, #4]
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lsr r10, r8, #8
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ldr r4, [r1]
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lsr r6, r9, #8
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orr r10, r10, r9, lsl #24
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ldr r5, [r2, #8]
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eor r11, r8, r10
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uhadd8 r7, r8, r10
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orr r6, r6, r5, lsl #24
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and r11, r11, lr
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uadd8 r7, r7, r11
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ldr r8, [r1, #4]
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usada8 r0, r4, r7, r0
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eor r7, r9, r6
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lsr r10, r5, #8
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and r7, r7, lr
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uhadd8 r4, r9, r6
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ldr r6, [r2, #12]
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uadd8 r4, r4, r7
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pld [r1, r3]
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orr r10, r10, r6, lsl #24
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usada8 r0, r8, r4, r0
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ldr r4, [r1, #8]
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eor r11, r5, r10
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ldrb r7, [r2, #16]
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and r11, r11, lr
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uhadd8 r8, r5, r10
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ldr r5, [r1, #12]
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uadd8 r8, r8, r11
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pld [r2, r3]
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lsr r10, r6, #8
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usada8 r0, r4, r8, r0
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orr r10, r10, r7, lsl #24
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subs r12, r12, #1
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eor r11, r6, r10
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add r1, r1, r3
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uhadd8 r9, r6, r10
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and r11, r11, lr
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uadd8 r9, r9, r11
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add r2, r2, r3
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usada8 r0, r5, r9, r0
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bgt 1b
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pop {r4-r11, pc}
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endfunc
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.macro usad_y2 p0, p1, p2, p3, n0, n1, n2, n3
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ldr \n0, [r2]
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eor \n1, \p0, \n0
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uhadd8 \p0, \p0, \n0
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and \n1, \n1, lr
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ldr \n2, [r1]
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uadd8 \p0, \p0, \n1
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ldr \n1, [r2, #4]
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usada8 r0, \p0, \n2, r0
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pld [r1, r3]
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eor \n3, \p1, \n1
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uhadd8 \p1, \p1, \n1
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and \n3, \n3, lr
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ldr \p0, [r1, #4]
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uadd8 \p1, \p1, \n3
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ldr \n2, [r2, #8]
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usada8 r0, \p1, \p0, r0
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pld [r2, r3]
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eor \p0, \p2, \n2
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uhadd8 \p2, \p2, \n2
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and \p0, \p0, lr
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ldr \p1, [r1, #8]
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uadd8 \p2, \p2, \p0
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ldr \n3, [r2, #12]
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usada8 r0, \p2, \p1, r0
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eor \p1, \p3, \n3
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uhadd8 \p3, \p3, \n3
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and \p1, \p1, lr
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ldr \p0, [r1, #12]
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uadd8 \p3, \p3, \p1
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add r1, r1, r3
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usada8 r0, \p3, \p0, r0
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add r2, r2, r3
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.endm
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function ff_pix_abs16_y2_armv6, export=1
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pld [r1]
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pld [r2]
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ldr r12, [sp]
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push {r4-r11, lr}
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mov r0, #0
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mov lr, #1
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orr lr, lr, lr, lsl #8
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orr lr, lr, lr, lsl #16
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ldr r4, [r2]
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ldr r5, [r2, #4]
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ldr r6, [r2, #8]
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ldr r7, [r2, #12]
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add r2, r2, r3
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1:
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usad_y2 r4, r5, r6, r7, r8, r9, r10, r11
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subs r12, r12, #2
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usad_y2 r8, r9, r10, r11, r4, r5, r6, r7
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bgt 1b
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pop {r4-r11, pc}
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endfunc
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function ff_pix_abs8_armv6, export=1
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pld [r2, r3]
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ldr r12, [sp]
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push {r4-r9, lr}
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mov r0, #0
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mov lr, #0
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ldrd_post r4, r5, r1, r3
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1:
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subs r12, r12, #2
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ldr r7, [r2, #4]
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ldr_post r6, r2, r3
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ldrd_post r8, r9, r1, r3
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usada8 r0, r4, r6, r0
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pld [r2, r3]
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usada8 lr, r5, r7, lr
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ldr r7, [r2, #4]
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ldr_post r6, r2, r3
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beq 2f
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ldrd_post r4, r5, r1, r3
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usada8 r0, r8, r6, r0
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pld [r2, r3]
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usada8 lr, r9, r7, lr
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b 1b
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2:
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usada8 r0, r8, r6, r0
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usada8 lr, r9, r7, lr
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add r0, r0, lr
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pop {r4-r9, pc}
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endfunc
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function ff_sse16_armv6, export=1
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ldr r12, [sp]
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push {r4-r9, lr}
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mov r0, #0
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1:
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ldrd r4, r5, [r1]
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ldr r8, [r2]
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uxtb16 lr, r4
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uxtb16 r4, r4, ror #8
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uxtb16 r9, r8
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uxtb16 r8, r8, ror #8
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ldr r7, [r2, #4]
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usub16 lr, lr, r9
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usub16 r4, r4, r8
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smlad r0, lr, lr, r0
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uxtb16 r6, r5
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uxtb16 lr, r5, ror #8
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uxtb16 r8, r7
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uxtb16 r9, r7, ror #8
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smlad r0, r4, r4, r0
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ldrd r4, r5, [r1, #8]
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usub16 r6, r6, r8
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usub16 r8, lr, r9
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ldr r7, [r2, #8]
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smlad r0, r6, r6, r0
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uxtb16 lr, r4
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uxtb16 r4, r4, ror #8
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uxtb16 r9, r7
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uxtb16 r7, r7, ror #8
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smlad r0, r8, r8, r0
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ldr r8, [r2, #12]
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usub16 lr, lr, r9
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usub16 r4, r4, r7
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smlad r0, lr, lr, r0
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uxtb16 r6, r5
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uxtb16 r5, r5, ror #8
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uxtb16 r9, r8
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uxtb16 r8, r8, ror #8
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smlad r0, r4, r4, r0
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usub16 r6, r6, r9
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usub16 r5, r5, r8
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smlad r0, r6, r6, r0
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add r1, r1, r3
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add r2, r2, r3
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subs r12, r12, #1
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smlad r0, r5, r5, r0
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bgt 1b
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pop {r4-r9, pc}
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endfunc
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