Rémi Denis-Courmont 529d423012 lavu/riscv: remove bespoke SH{1,2,3}ADD assembler ...

configure checks that the assembler supports the B extension (or rather
its constituents) anyway. These macros were dodging sanity checks for
unsupported instructions and nothing else.

2024-07-25 18:55:48 +03:00

..

asm.S

lavu/riscv: remove bespoke SH{1,2,3}ADD assembler

2024-07-25 18:55:48 +03:00

bswap_rvb.S

…

bswap.h

lavu/riscv: use Zbb REV8 at run-time

2024-06-11 20:12:37 +03:00

cpu_common.c

riscv: probe for Zbb extension at load time

2024-06-11 20:12:37 +03:00

cpu.c

lavu/riscv: do not fallback to AT_HWCAP auxillary vector

2024-07-22 19:43:51 +03:00

cpu.h

avutil/riscv/cpu: fix __riscv_v_min_vlen typo

2024-06-26 12:50:02 +02:00

fixed_dsp_init.c

…

fixed_dsp_rvv.S

lavu/riscv: require B or zba explicitly

2024-07-25 18:55:48 +03:00

float_dsp_init.c

lavu/float_dsp: R-V V scalarproduct_double

2024-05-31 22:22:43 +03:00

float_dsp_rvv.S

lavu/riscv: require B or zba explicitly

2024-07-25 18:55:48 +03:00

intmath.h

lavu/riscv: use Zbb CLZ/CTZ/CLZW/CTZW at run-time

2024-06-11 20:12:37 +03:00

lls_init.c

lavu/lls: R-V V update_lls

2024-06-01 18:05:58 +03:00

lls_rvv.S

lavu/lls: remove useless VSETVL

2024-06-29 21:03:44 +03:00

Makefile

riscv: probe for Zbb extension at load time

2024-06-11 20:12:37 +03:00

timer.h

…