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bf8bb94322
* qatar/master: ffmpeg: get rid of the -vglobal option. dct32: Add AVX implementation of 32-point DCT dct32: Change pass 6 permutation to allow for AVX implementation dct32: port SSE 32-point DCT to YASM multiple inclusion guard cleanup avio: document buffer must created with av_malloc() and friends avio: check AVIOContext malloc failure swscale: point out an alternative to sws_getContext svq3: Do initialization after parsing the extradata add changelog entries for 0.7_beta2 mp3lame: add #include required for AV_RB32 macro. Conflicts: Changelog libavcodec/svq3.c libavcodec/x86/dct32_sse.c libavfilter/vsrc_buffer.h Merged-by: Michael Niedermayer <michaelni@gmx.at>
93 lines
3.5 KiB
C
93 lines
3.5 KiB
C
/*
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* Copyright (C) 2010 Mans Rullgard <mans@mansr.com>
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*
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* This file is part of FFmpeg.
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*
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* FFmpeg is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* FFmpeg is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with FFmpeg; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef AVCODEC_ARM_VP56_ARITH_H
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#define AVCODEC_ARM_VP56_ARITH_H
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#if HAVE_ARMV6 && HAVE_INLINE_ASM
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#define vp56_rac_get_prob vp56_rac_get_prob_armv6
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static inline int vp56_rac_get_prob_armv6(VP56RangeCoder *c, int pr)
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{
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unsigned shift = ff_vp56_norm_shift[c->high];
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unsigned code_word = c->code_word << shift;
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unsigned high = c->high << shift;
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unsigned bit;
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__asm__ volatile ("adds %3, %3, %0 \n"
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"cmpcs %7, %4 \n"
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"ldrcsh %2, [%4], #2 \n"
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"rsb %0, %6, #256 \n"
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"smlabb %0, %5, %6, %0 \n"
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"rev16cs %2, %2 \n"
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"orrcs %1, %1, %2, lsl %3 \n"
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"subcs %3, %3, #16 \n"
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"lsr %0, %0, #8 \n"
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"cmp %1, %0, lsl #16 \n"
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"subge %1, %1, %0, lsl #16 \n"
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"subge %0, %5, %0 \n"
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"movge %2, #1 \n"
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"movlt %2, #0 \n"
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: "=&r"(c->high), "=&r"(c->code_word), "=&r"(bit),
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"+&r"(c->bits), "+&r"(c->buffer)
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: "r"(high), "r"(pr), "r"(c->end - 1),
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"0"(shift), "1"(code_word));
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return bit;
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}
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#define vp56_rac_get_prob_branchy vp56_rac_get_prob_branchy_armv6
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static inline int vp56_rac_get_prob_branchy_armv6(VP56RangeCoder *c, int pr)
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{
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unsigned shift = ff_vp56_norm_shift[c->high];
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unsigned code_word = c->code_word << shift;
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unsigned high = c->high << shift;
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unsigned low;
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unsigned tmp;
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__asm__ volatile ("adds %3, %3, %0 \n"
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"cmpcs %7, %4 \n"
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"ldrcsh %2, [%4], #2 \n"
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"rsb %0, %6, #256 \n"
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"smlabb %0, %5, %6, %0 \n"
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"rev16cs %2, %2 \n"
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"orrcs %1, %1, %2, lsl %3 \n"
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"subcs %3, %3, #16 \n"
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"lsr %0, %0, #8 \n"
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"lsl %2, %0, #16 \n"
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: "=&r"(low), "+&r"(code_word), "=&r"(tmp),
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"+&r"(c->bits), "+&r"(c->buffer)
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: "r"(high), "r"(pr), "r"(c->end - 1), "0"(shift));
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if (code_word >= tmp) {
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c->high = high - low;
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c->code_word = code_word - tmp;
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return 1;
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}
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c->high = low;
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c->code_word = code_word;
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return 0;
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}
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#endif
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#endif /* AVCODEC_ARM_VP56_ARITH_H */
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