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https://github.com/FFmpeg/FFmpeg.git
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3f87f39cb8
Use the new x86inc features to support 64-bit Windows on all non-x264 nasm assembly code as well. Patch by John Adcock, dscaler.johnad AT googlemail DOT com. Win64 changes originally by Anton Mitrofanov. x86util changes mostly by Holger Lubitz. Originally committed as revision 19580 to svn://svn.ffmpeg.org/ffmpeg/trunk
474 lines
11 KiB
NASM
474 lines
11 KiB
NASM
;******************************************************************************
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;* FFT transform with SSE/3DNow optimizations
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;* Copyright (c) 2008 Loren Merritt
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;*
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;* This file is part of FFmpeg.
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;*
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;* FFmpeg is free software; you can redistribute it and/or
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;* modify it under the terms of the GNU Lesser General Public
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;* License as published by the Free Software Foundation; either
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;* version 2.1 of the License, or (at your option) any later version.
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;*
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;* FFmpeg is distributed in the hope that it will be useful,
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;* but WITHOUT ANY WARRANTY; without even the implied warranty of
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;* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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;* Lesser General Public License for more details.
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;*
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;* You should have received a copy of the GNU Lesser General Public
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;* License along with FFmpeg; if not, write to the Free Software
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;* 51, Inc., Foundation Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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;******************************************************************************
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; These functions are not individually interchangeable with the C versions.
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; While C takes arrays of FFTComplex, SSE/3DNow leave intermediate results
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; in blocks as conventient to the vector size.
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; i.e. {4x real, 4x imaginary, 4x real, ...} (or 2x respectively)
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%include "x86inc.asm"
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SECTION_RODATA
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%define M_SQRT1_2 0.70710678118654752440
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ps_root2: times 4 dd M_SQRT1_2
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ps_root2mppm: dd -M_SQRT1_2, M_SQRT1_2, M_SQRT1_2, -M_SQRT1_2
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ps_m1p1: dd 1<<31, 0
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%assign i 16
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%rep 13
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cextern ff_cos_ %+ i
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%assign i i<<1
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%endrep
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%ifdef ARCH_X86_64
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%define pointer dq
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%else
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%define pointer dd
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%endif
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%macro IF0 1+
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%endmacro
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%macro IF1 1+
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%1
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%endmacro
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section .text align=16
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%macro T2_3DN 4 ; z0, z1, mem0, mem1
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mova %1, %3
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mova %2, %1
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pfadd %1, %4
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pfsub %2, %4
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%endmacro
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%macro T4_3DN 6 ; z0, z1, z2, z3, tmp0, tmp1
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mova %5, %3
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pfsub %3, %4
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pfadd %5, %4 ; {t6,t5}
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pxor %3, [ps_m1p1 GLOBAL] ; {t8,t7}
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mova %6, %1
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pswapd %3, %3
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pfadd %1, %5 ; {r0,i0}
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pfsub %6, %5 ; {r2,i2}
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mova %4, %2
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pfadd %2, %3 ; {r1,i1}
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pfsub %4, %3 ; {r3,i3}
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SWAP %3, %6
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%endmacro
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; in: %1={r0,i0,r1,i1} %2={r2,i2,r3,i3}
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; out: %1={r0,r1,r2,r3} %2={i0,i1,i2,i3}
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%macro T4_SSE 3
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mova %3, %1
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shufps %1, %2, 0x64 ; {r0,i0,r3,i2}
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shufps %3, %2, 0xce ; {r1,i1,r2,i3}
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mova %2, %1
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addps %1, %3 ; {t1,t2,t6,t5}
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subps %2, %3 ; {t3,t4,t8,t7}
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mova %3, %1
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shufps %1, %2, 0x44 ; {t1,t2,t3,t4}
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shufps %3, %2, 0xbe ; {t6,t5,t7,t8}
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mova %2, %1
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addps %1, %3 ; {r0,i0,r1,i1}
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subps %2, %3 ; {r2,i2,r3,i3}
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mova %3, %1
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shufps %1, %2, 0x88 ; {r0,r1,r2,r3}
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shufps %3, %2, 0xdd ; {i0,i1,i2,i3}
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SWAP %2, %3
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%endmacro
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%macro T8_SSE 6 ; r0,i0,r1,i1,t0,t1
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mova %5, %3
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shufps %3, %4, 0x44 ; {r4,i4,r6,i6}
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shufps %5, %4, 0xee ; {r5,i5,r7,i7}
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mova %6, %3
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subps %3, %5 ; {r5,i5,r7,i7}
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addps %6, %5 ; {t1,t2,t3,t4}
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mova %5, %3
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shufps %5, %5, 0xb1 ; {i5,r5,i7,r7}
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mulps %3, [ps_root2mppm GLOBAL] ; {-r5,i5,r7,-i7}
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mulps %5, [ps_root2 GLOBAL]
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addps %3, %5 ; {t8,t7,ta,t9}
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mova %5, %6
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shufps %6, %3, 0x36 ; {t3,t2,t9,t8}
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shufps %5, %3, 0x9c ; {t1,t4,t7,ta}
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mova %3, %6
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addps %6, %5 ; {t1,t2,t9,ta}
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subps %3, %5 ; {t6,t5,tc,tb}
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mova %5, %6
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shufps %6, %3, 0xd8 ; {t1,t9,t5,tb}
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shufps %5, %3, 0x8d ; {t2,ta,t6,tc}
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mova %3, %1
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mova %4, %2
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addps %1, %6 ; {r0,r1,r2,r3}
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addps %2, %5 ; {i0,i1,i2,i3}
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subps %3, %6 ; {r4,r5,r6,r7}
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subps %4, %5 ; {i4,i5,i6,i7}
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%endmacro
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; scheduled for cpu-bound sizes
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%macro PASS_SMALL 3 ; (to load m4-m7), wre, wim
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IF%1 mova m4, Z(4)
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IF%1 mova m5, Z(5)
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mova m0, %2 ; wre
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mova m2, m4
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mova m1, %3 ; wim
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mova m3, m5
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mulps m2, m0 ; r2*wre
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IF%1 mova m6, Z(6)
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mulps m3, m1 ; i2*wim
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IF%1 mova m7, Z(7)
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mulps m4, m1 ; r2*wim
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mulps m5, m0 ; i2*wre
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addps m2, m3 ; r2*wre + i2*wim
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mova m3, m1
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mulps m1, m6 ; r3*wim
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subps m5, m4 ; i2*wre - r2*wim
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mova m4, m0
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mulps m3, m7 ; i3*wim
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mulps m4, m6 ; r3*wre
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mulps m0, m7 ; i3*wre
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subps m4, m3 ; r3*wre - i3*wim
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mova m3, Z(0)
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addps m0, m1 ; i3*wre + r3*wim
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mova m1, m4
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addps m4, m2 ; t5
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subps m1, m2 ; t3
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subps m3, m4 ; r2
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addps m4, Z(0) ; r0
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mova m6, Z(2)
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mova Z(4), m3
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mova Z(0), m4
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mova m3, m5
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subps m5, m0 ; t4
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mova m4, m6
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subps m6, m5 ; r3
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addps m5, m4 ; r1
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mova Z(6), m6
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mova Z(2), m5
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mova m2, Z(3)
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addps m3, m0 ; t6
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subps m2, m1 ; i3
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mova m7, Z(1)
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addps m1, Z(3) ; i1
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mova Z(7), m2
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mova Z(3), m1
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mova m4, m7
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subps m7, m3 ; i2
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addps m3, m4 ; i0
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mova Z(5), m7
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mova Z(1), m3
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%endmacro
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; scheduled to avoid store->load aliasing
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%macro PASS_BIG 1 ; (!interleave)
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mova m4, Z(4) ; r2
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mova m5, Z(5) ; i2
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mova m2, m4
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mova m0, [wq] ; wre
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mova m3, m5
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mova m1, [wq+o1q] ; wim
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mulps m2, m0 ; r2*wre
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mova m6, Z(6) ; r3
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mulps m3, m1 ; i2*wim
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mova m7, Z(7) ; i3
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mulps m4, m1 ; r2*wim
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mulps m5, m0 ; i2*wre
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addps m2, m3 ; r2*wre + i2*wim
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mova m3, m1
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mulps m1, m6 ; r3*wim
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subps m5, m4 ; i2*wre - r2*wim
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mova m4, m0
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mulps m3, m7 ; i3*wim
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mulps m4, m6 ; r3*wre
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mulps m0, m7 ; i3*wre
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subps m4, m3 ; r3*wre - i3*wim
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mova m3, Z(0)
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addps m0, m1 ; i3*wre + r3*wim
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mova m1, m4
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addps m4, m2 ; t5
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subps m1, m2 ; t3
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subps m3, m4 ; r2
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addps m4, Z(0) ; r0
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mova m6, Z(2)
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mova Z(4), m3
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mova Z(0), m4
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mova m3, m5
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subps m5, m0 ; t4
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mova m4, m6
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subps m6, m5 ; r3
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addps m5, m4 ; r1
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IF%1 mova Z(6), m6
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IF%1 mova Z(2), m5
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mova m2, Z(3)
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addps m3, m0 ; t6
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subps m2, m1 ; i3
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mova m7, Z(1)
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addps m1, Z(3) ; i1
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IF%1 mova Z(7), m2
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IF%1 mova Z(3), m1
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mova m4, m7
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subps m7, m3 ; i2
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addps m3, m4 ; i0
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IF%1 mova Z(5), m7
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IF%1 mova Z(1), m3
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%if %1==0
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mova m4, m5 ; r1
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mova m0, m6 ; r3
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unpcklps m5, m1
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unpckhps m4, m1
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unpcklps m6, m2
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unpckhps m0, m2
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mova m1, Z(0)
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mova m2, Z(4)
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mova Z(2), m5
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mova Z(3), m4
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mova Z(6), m6
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mova Z(7), m0
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mova m5, m1 ; r0
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mova m4, m2 ; r2
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unpcklps m1, m3
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unpckhps m5, m3
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unpcklps m2, m7
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unpckhps m4, m7
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mova Z(0), m1
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mova Z(1), m5
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mova Z(4), m2
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mova Z(5), m4
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%endif
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%endmacro
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%macro PUNPCK 3
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mova %3, %1
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punpckldq %1, %2
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punpckhdq %3, %2
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%endmacro
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INIT_XMM
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%define Z(x) [r0+mmsize*x]
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align 16
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fft4_sse:
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mova m0, Z(0)
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mova m1, Z(1)
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T4_SSE m0, m1, m2
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mova Z(0), m0
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mova Z(1), m1
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ret
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align 16
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fft8_sse:
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mova m0, Z(0)
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mova m1, Z(1)
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T4_SSE m0, m1, m2
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mova m2, Z(2)
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mova m3, Z(3)
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T8_SSE m0, m1, m2, m3, m4, m5
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mova Z(0), m0
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mova Z(1), m1
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mova Z(2), m2
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mova Z(3), m3
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ret
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align 16
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fft16_sse:
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mova m0, Z(0)
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mova m1, Z(1)
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T4_SSE m0, m1, m2
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mova m2, Z(2)
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mova m3, Z(3)
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T8_SSE m0, m1, m2, m3, m4, m5
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mova m4, Z(4)
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mova m5, Z(5)
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mova Z(0), m0
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mova Z(1), m1
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mova Z(2), m2
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mova Z(3), m3
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T4_SSE m4, m5, m6
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mova m6, Z(6)
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mova m7, Z(7)
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T4_SSE m6, m7, m0
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PASS_SMALL 0, [ff_cos_16 GLOBAL], [ff_cos_16+16 GLOBAL]
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ret
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INIT_MMX
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%macro FFT48_3DN 1
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align 16
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fft4%1:
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T2_3DN m0, m1, Z(0), Z(1)
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mova m2, Z(2)
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mova m3, Z(3)
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T4_3DN m0, m1, m2, m3, m4, m5
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PUNPCK m0, m1, m4
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PUNPCK m2, m3, m5
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mova Z(0), m0
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mova Z(1), m4
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mova Z(2), m2
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mova Z(3), m5
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ret
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align 16
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fft8%1:
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T2_3DN m0, m1, Z(0), Z(1)
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mova m2, Z(2)
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mova m3, Z(3)
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T4_3DN m0, m1, m2, m3, m4, m5
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mova Z(0), m0
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mova Z(2), m2
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T2_3DN m4, m5, Z(4), Z(5)
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T2_3DN m6, m7, Z(6), Z(7)
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pswapd m0, m5
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pswapd m2, m7
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pxor m0, [ps_m1p1 GLOBAL]
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pxor m2, [ps_m1p1 GLOBAL]
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pfsub m5, m0
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pfadd m7, m2
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pfmul m5, [ps_root2 GLOBAL]
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pfmul m7, [ps_root2 GLOBAL]
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T4_3DN m1, m3, m5, m7, m0, m2
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mova Z(5), m5
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mova Z(7), m7
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mova m0, Z(0)
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mova m2, Z(2)
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T4_3DN m0, m2, m4, m6, m5, m7
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PUNPCK m0, m1, m5
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PUNPCK m2, m3, m7
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mova Z(0), m0
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mova Z(1), m5
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mova Z(2), m2
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mova Z(3), m7
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PUNPCK m4, Z(5), m5
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PUNPCK m6, Z(7), m7
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mova Z(4), m4
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mova Z(5), m5
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mova Z(6), m6
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mova Z(7), m7
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ret
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%endmacro
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FFT48_3DN _3dn2
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%macro pswapd 2
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%ifidn %1, %2
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movd [r0+12], %1
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punpckhdq %1, [r0+8]
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%else
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movq %1, %2
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psrlq %1, 32
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punpckldq %1, %2
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%endif
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%endmacro
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FFT48_3DN _3dn
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%define Z(x) [zq + o1q*(x&6)*((x/6)^1) + o3q*(x/6) + mmsize*(x&1)]
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%macro DECL_PASS 2+ ; name, payload
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align 16
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%1:
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DEFINE_ARGS z, w, n, o1, o3
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lea o3q, [nq*3]
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lea o1q, [nq*8]
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shl o3q, 4
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.loop:
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%2
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add zq, mmsize*2
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add wq, mmsize
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sub nd, mmsize/8
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jg .loop
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rep ret
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%endmacro
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INIT_XMM
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DECL_PASS pass_sse, PASS_BIG 1
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DECL_PASS pass_interleave_sse, PASS_BIG 0
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INIT_MMX
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%define mulps pfmul
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%define addps pfadd
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%define subps pfsub
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%define unpcklps punpckldq
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%define unpckhps punpckhdq
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DECL_PASS pass_3dn, PASS_SMALL 1, [wq], [wq+o1q]
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DECL_PASS pass_interleave_3dn, PASS_BIG 0
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%define pass_3dn2 pass_3dn
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%define pass_interleave_3dn2 pass_interleave_3dn
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%macro DECL_FFT 2-3 ; nbits, cpu, suffix
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%xdefine list_of_fft fft4%2, fft8%2
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%if %1==5
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%xdefine list_of_fft list_of_fft, fft16%2
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%endif
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%assign n 1<<%1
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%rep 17-%1
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%assign n2 n/2
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%assign n4 n/4
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%xdefine list_of_fft list_of_fft, fft %+ n %+ %3%2
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align 16
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fft %+ n %+ %3%2:
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call fft %+ n2 %+ %2
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add r0, n*4 - (n&(-2<<%1))
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call fft %+ n4 %+ %2
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add r0, n*2 - (n2&(-2<<%1))
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call fft %+ n4 %+ %2
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sub r0, n*6 + (n2&(-2<<%1))
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lea r1, [ff_cos_ %+ n GLOBAL]
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mov r2d, n4/2
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jmp pass%3%2
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%assign n n*2
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%endrep
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%undef n
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%ifidn __OUTPUT_FORMAT__,macho64
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section .rodata
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%endif
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align 8
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dispatch_tab%3%2: pointer list_of_fft
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section .text
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; On x86_32, this function does the register saving and restoring for all of fft.
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; The others pass args in registers and don't spill anything.
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cglobal fft_dispatch%3%2, 2,5,8, z, nbits
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lea r2, [dispatch_tab%3%2 GLOBAL]
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mov r2, [r2 + (nbitsq-2)*gprsize]
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call r2
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RET
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%endmacro ; DECL_FFT
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DECL_FFT 5, _sse
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DECL_FFT 5, _sse, _interleave
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DECL_FFT 4, _3dn
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DECL_FFT 4, _3dn, _interleave
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DECL_FFT 4, _3dn2
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DECL_FFT 4, _3dn2, _interleave
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